ECS Day 3: Signs of life after all

by Michael A. Fury, Techcet Group

May 29, 2009 – Day 3 of the ECS Spring 2009 Meeting showed signs of normalization: good sized audiences in right-sized rooms, and presentations proceeding as scheduled. One artifact of holding such a large meeting in the San Francisco Hilton is that the symposium rooms are spread out across many floors; perhaps earlier impressions of the meeting and attendance, to the extent that they may have sounded negative, may have been due simply to my inadequate sampling of the full scope of the meeting.

M. Dankerl of the Schottky Institute in Munich demonstrated a novel all-diamond transistor [symposium/abstract ID: C2-605], an important step in developing a semiconductor-biological cell interface for fundamental research on neuronal networks and eventual implementation in medical prostheses. The hydrogen-terminated diamond surface is used as an electrode in a solution gate field effect transistor (SGFET) design. In separate demonstrations, two types of cells were cultured on the diamond surface. The ionic nature of the cell response to chemical and electrical stimuli makes it detectable via the ion sensitivity of the diamond surface.

W.H. Lee of National Cheng Kung University in Taiwan reduced the charge trapping at the pentacene-dielectric interface of an organic TFT using CMP of the TiO2 composite dielectric layer [E3-920]. The smoother interface resulted in a 100× increase in the on/off current ratio and a 50% increase in electron mobility. In an odd twist, the CMP process required a stacked pad in which the soft pad was stacked on top of the hard pad.

J.-K. Ahn of Chungnam National University in Korea presented some early work on In3SbTe2 (IST) as an alternative to the more widely-used GST phase-change material for both DVD-RW and PRAM applications [F1-1009]. Feasibility was shown for MOCVD deposition at 225°C with good step coverage, though deposition rates were only 5Å/min. Both IST and GST melt at ~630°C, but the amorphous phase transition for IST occurs near 290°C vs. 130°C for GST. Phase-change life cycle testing has yet to begin.

W.-C. Li of National Taiwan University demonstrated the use of high-k HfAlOx dielectric with a Pt gate electrode in a n-Si/SiO2/HfAlOx/Al2O3/Pt stack structure [E3-764]. The HfAlOx material is deposited as HfO2 and forms a 3nm thick nanocrystalline layer on annealing for 1 minute at 900°C-1000°C in N2. A reasonably large memory window was observed even after 7 days of charge retention, opening the possibility for future NAND applications.

H. Harris of Texas A&M gave an overview of selected issues in the integration of SiGe PMOS devices with NMOS devices [E1-720]. One problem area is the structure deformation at the Si-STI interface caused by the introduction of the SiGe layer; another is the complexity due to the different gate dielectric and electrode materials required for the NMOS device, and the difficulty of concurrently etching and stopping appropriately both the PMOS and the NMOS gate stacks. A suitable process resolution was demonstrated, but details were withheld. Nonetheless, feasibility for a CMOS-gate-first process beyond 22nm was claimed.

A. Veloso of IMEC talked about the characteristics and integration challenges of various modifications of the FinFET variety of multi-gate FET (MuGFET) designs for post-32nm device architecture [E9-935]. This scaling route follows conventional CMOS processing to a large degree, and for some devices can be implemented on either bulk Si or on SOI. Spacer defined patterning is required to fabricate the narrow (<10nm) fins, but such techniques have been well-established over 30 years of practice, though never at this scale. Even with this radical architecture change, integration of the panoply of separate gate dielectric and electrode materials for the PMOS and NMOS devices is an issue that must still be faced.

One feature of the Meeting was the First International Symposium on Graphene and Emerging Materials for Post-CMOS Applications. While many papers were presented on a variety of materials in addition to graphene, one that caught my attention was on graphene aerogels by J. Wang of Tyco Electronics [H10-1326]. The material is fabricated from a graphite oxide dispersion in water, which is then reduced to graphene at 300°C in Ar. The reduced material has a conductivity six orders of magnitude greater than the oxide. Its I-V voltammograms indicate a constant rate for both charging and discharging, desirable for capacitor applications. The calculated specific capacitance is on the order of 80 Farads per gram.

The complete ECS Spring 2009 abstract directory can be found here.


Michael A. Fury, Ph.D, is senior technology analyst at Techcet Group, LLC, P.O. Box 29, Del Mar, CA 92014; email mfury@techcet.com.

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