Micron sampling new NAND+DRAM multichip package

November 4, 2009 – Micron Technology says it is now sampling a multichip package (MCP) combing its 34nm-based 4Gb SLC NAND flash and 50nm-based 2Gb low-power DDR DRAM memories, a combination it says offers better cost and power savings for mobile devices.

The new MCP targets "mainstream densities in today’s mobile devices," but the company says it can support higher densities as well (up to 8Gb NAND and 8Gb LPDDR) as devices integrate more sophisticated multimedia functionality.

"We are providing customers with the most advanced solution available in NAND-based MCPs," said Eric Spanneut, director of mobile memory marketing at Samsung, in a statement. "By combining the industry’s leading NAND and DRAM processes within our new generation of MCPs, we are able to easily accommodate the shift to high-density NAND devices as the industry progresses toward multifunction mobile devices.

The MCP is the company’s first monolithic 2Gb LPDRAM, according to Spanneut, in an interview on Micron’s Web site. He notes that handset vendor adoption of a DDR2 version of the technology isn’t expected until 2H10, so the DDR version will likely take the lion’s share of volumes "for the next three to four years."


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