ASMC: Inside yield enhancement & methodologies

by Gary Green, co-chair, yield enhancement/methodologies sessions, ASMC

July 14, 2010 – This year’s Yield Enhancement/Methodologies sessions at ASMC2010 featured a variety of innovative techniques aimed at faster root cause analysis, new methods in analyzing contact failures using e-beam and TEM tools, the use of stackable test chips to increase test coverage while reducing the number of test wafers, using print simulations to correct potential problems prior to first mask and the use of embedded test macros to more accurately capture product characteristics as compared with scribe line monitoring. Additional topics included new topcoat-less resist technology for immersion lithography aimed at the 22nm node and a new multi-layer tool commonality technique to facilitate problem tool identification.

Among evolving yield strategies, volume diagnostics looks like it is starting to resonate as a viable logic yield analysis tool, especially for new design ramps. In two papers presented at the conference, ST/Synopsys and IBM reported significant progress in achieving faster time to results in diagnosing systematic logic failure mechanisms that were not easily detectable by traditional failure analysis.

The ability to incorporate design-centric data into the failure analysis flow with defect, parametric and test fail data is reported to enable much faster drill down to the likely failure cells and nets using die and wafer level statistics. Software tools are now available to link the massive amounts of design and test data that can identify these probable failure mechanisms quickly. Volume diagnostics is a method of gathering large amounts of transition and stuck-at faults at test and then statistically prioritizing the failures by net and cell names which can be associated with exact physical locations on a die or across a wafer. These locations are forwarded to failure analysis to validate failure mechanisms.

In ramp stage, fast feedback of possible design issues is key to maintaining time-to-market schedules and, in fact, may be critical to ultimate product profitability. One of the presenting IDMs discussed several examples where a factor-of-ten improvement in diagnosis speed and subsequent feedback to design (from 30 to 3 days) was achieved. Although this technique requires connection to a wider variety of data sources, including the design database, new product teams using this more inclusive methodology may enjoy a competitive advantage over traditional analysis.

In a paper on the use of topcoat-less resists, Nikon Precision indicated that a viable immersion lithography solution for the 22nm node already exists as companies await the arrival of next generation EUVL tools. Test data showed that using topcoat-less resists is at least comparable to current topcoat resists and have the advantage of lower material costs and of potentially eliminating several steps in the litho process, resulting in a lower cost-of ownership for this process step.

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 Gary Green is Principal at Green Technology Consulting. He is serving as a co-chair of the Yield Enhancement/Methodologies sessions at ASMC2010 in San Francisco.

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