Freescale licenses RCP to Nepes, brings redistributed chip packaging to 300mm in Singapore

(September 13, 2010 – BUSINESS WIRE) — Freescale Semiconductor will license its redistributed chip packaging (RCP) technology to Nepes Corporation, a Korean semiconductor parts and materials specialist. Nepes and Freescale will also collaborate on RCP development.

Nepes installed the 300mm equipment set and manufacturing process capable of multiple-layer single-die and multi-die system-in-package (SiP) solutions at its facility in Singapore (Nepes Pte) earlier this year. The technology start-up at Nepes is in progress with a volume ramp forecast for the first quarter of 2011. Using RCP on 300mm wafers is expected to lower costs for the advanced packaging technology.

Freescale and Nepes are also collaborating in a joint development effort to further enhance the capabilities of the RCP technology. Development activities are expected to continue at both Freescale’s US RCP development facility in Tempe, AZ and at Nepes’ facility in Singapore. Advanced Packaging blogger Dr. Phil Garrou notes that, "During the recent hard economic times, Freescale scaled back their process work and eventually licensed their process to Nepes." (Read Insights from the Leading Edge, Dr. Garrou’s blog, here)

The collaboration will enable single die, 2D, and 3D systems-in-package targeted at a broad range of industries and applications.

Freescale, which developed and introduced the now widely deployed ball grid array (BGA) packaging technology, announced the RCP technology in 2006. Fan-out RCP integrates semiconductor packaging as a functional part of the die and system solution. RCP is a substrate-less embedded chip package that offers a low-cost, high performance, integrated alternative to current wire bond BGA and flip chip BGA packaging. Semiconductor devices are encapsulated into panels while routing of signals, power and ground is built directly on the panel. The RCP panel and signal buildup lower the cost of the package by eliminating wafer bumping and substrates, thereby enabling large scale assembly in panel form. The buildup provides better routing and integration capabilities than traditional printed circuit boards (PCB) or high density interconnect PCBs. By eliminating chip to package bumping, the package is inherently lead-free and the stress of the package is reduced enabling ultra-low-k device compatibility.

It addresses some of the significant limitations associated with previous generations of packaging technologies by eliminating higher cost wire bonds, package substrates and flip chip bumps. In addition, RCP does not utilize blind vias or require thinned die to achieve thin profiles. These advancements simplify assembly, lower costs and provide compatibility with advanced wafer manufacturing processes utilizing low-k interlayer dielectrics.

The RCP fan-out package provides solutions for both highly sensitive analog devices and digital platforms. The technology is compatible with small and larger package sizes. RCP accommodates single and multiple routing layers to optimize package size, performance, die size range of I/O and cost.

Research and Markets recently published a report on embedded and fan-out wafer-level packaging (WLP)

Key advantages of RCP include:

  • Improved electrical performance resulting from shortened routing distances and reduced contact resistance.
  • Reduced cost due to elimination of wirebonds, large batch processing and simplified assembly process.
  • Reduced assembly stress suitable for packaging low-k dielectrics increasingly common on modern semiconductor die.
  • RCP results in a “green” product, halogen and lead-free and RoHS compliant.
  • Enables the reduction of die size due to an improvement in package performance.
  • RCP technology can be highly integrated allowing for single-die, multi-die SiP, stacked packages and other 3D integrated packaging solutions.

Nepes is a major back-end supplier in the system LSI semiconductor market, providing technology ranging from display driver ICs to wafer level packages on 8" and 12" wafers. Nepes, based in South Korea and Singapore, performs 300mm flip-chip bumping (lead-free and eutectic solder), wafer level BGA (WLBGA), Au redistributed layer, 40um pitch micro bumping, and copper pillar. For more information, visit and

Freescale Semiconductor designs and manufactures embedded semiconductors for the automotive, consumer, industrial and networking markets. Learn more at

Also read:

Convergence of 3D integrated packaging and 3D TSV ICs by Navjot Chhabra, Freescale Semiconductor

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