(October 27, 2010) — Xilinx Inc. (Nasdaq: XLNX) debuted a stacked silicon interconnect technology for breakthrough capacity, bandwidth and power savings using multiple FPGA die in a single package. The stacked silicon package suits applications that require high-transistor and logic density, as well as intense computational and bandwidth performance.
In an interview with Debra Vogler, senior technical editor, Liam Madden, corporate VP, FPGA development and silicon technology at Xilinx, describes the details of the silicon interposer. Madden explains that the TSVs only carry power and I/O signals from the package through the interposer to the FPGA. Madden also explains that using an interposer simplifies the CAD flow. Another unintended advantage of using the interposer is the stress relief provided to the low-k dielectric at the surface of the FPGA.
By embracing 3D packaging technologies and through-silicon vias (TSV) for its 28nm 7 series FPGAs, Xilinx’s Targeted Design Platforms can address systems with resource requirements that are more than double the reach of the largest single-die FPGAs. This innovative platform approach enables Xilinx to overcome the boundaries of Moore’s Law with power, bandwidth and density optimization for the large-scale-integration. Insights from the Leading Edge blogger, Dr. Phil Garrou, says that "the true 3D aficionado has been waiting for the first true commercial product announcement," and assesses the technology announcement on these grounds here.
“One of the ways the 28nm Xilinx 7 series FPGAs extend the range of applications programmable logic can address is by offering industry-leading capacity of up to 2 million logic cells, with use of stacked silicon interconnect packaging,” said Vincent Tong, Xilinx SVP.
The 3D packaging approach was developed over 5 years with internal Xilinx resources as well as technology from Amkor (AMKR) and TSMC. The device is made possible by micro-bump assembly by Amkor, advanced technology from TSMC and patented FPGA architectural innovations from Xilinx that deliver lower levels of power consumption, system cost and circuit board complexity compared to using multiple FPGAs, each in their own package, for the same application. “Compared with traditional monolithic FPGAs, multi-chip packaging approach is an innovative way to deliver large-scale programmability with favorable yield, reliability, thermal gradient, and stress tolerance characteristics,” said Shang-yi Chiang, SVP of R&D at TSMC. “By using through-silicon via technology and silicon interposer to implement a stacked silicon interconnect approach, Xilinx expects to reduce risks and is on the way to volume production with well-designed test vehicle runs that meet the company’s criteria for design enablement, manufacturability validation, and reliability assessment.”
With software support available in ISE Design Suite 13.1,which is currently available to beta customers, the 28nm Virtex-7 LX2000T device will be a multi-die FPGA that provides more than 3.5× the logic capacity of the largest current-generation Xilinx 40nm FPGA with serial transceivers and 2.8× the logic capacity of the largest competing 28nm FPGA with serial transceivers. The technology’s ultra high-bandwidth, low-latency and low-power interconnect allows customers to implement applications applying the same approaches used for large monolithic FPGA devices, using the software’s built-in auto partitioning capabilities for push-button ease-of use, or hierarchical and team-based design techniques for the highest performance and productivity.
Within the Xilinx stacked silicon interconnect structure, data flows between a set of adjacent FPGA die across more than 10,000 routing connections. Compared with having to use standard I/O connections to integrate two FPGAs together on a circuit board, stacked silicon interconnect technology provides over 100X the die-to-die connectivity bandwidth per watt, at one-fifth the latency, without consuming any high-speed serial or parallel I/O resources. By having die sit adjacent to each other and interfaced to the ball-grid-array, Xilinx can avoid the thermal flux and design tool flow issues that would be introduced had a purely vertical die-stacking approach been taken. Xilinx’s choice of 28nm HPL (high-performance, low-power) process technology for the base FPGA device provides a comfortable power budget in the package for integrating FPGA die.
“The availability of proven TSV technology along with low-latency interposer structures is being used effectively by Xilinx to expand the capabilities of their FPGA products,” said Dr. Handel H. Jones founder and CEO of IBS, Inc (Los Gatos, CA). “The technologies used by Xilinx have been used in the high-volume manufacturing environment, with the expectation that the quality and reliability of the finished products will be high, where customer risks are very low.”
Software support will be available in ISE Design Suite 13.1, which is currently available to beta customers. Initial devices will be available in H2 2011. For more technical information including white papers, visit http://www.xilinx.com/stacked-silicon.