by Karey Holland, Techcet Group
November 19, 2010 – A large turnout of more than 250 people attended this year’s International Conference on Planarization Technology (ICPT, Nov. 15-16 in Phoenix), 35 more than preregistered, and the Biltmore Hotel had to hunt up more chairs for the crowd. The presentations were well balanced between academics, chipmakers, and materials suppliers, with excellent representation from the international community — and most satisfyingly, all emphasized technology and not one presentation appeared to be a "sales pitch." (Of course, some presentations were works or learning in progress, and others may have been "red herring" work abandoned in the fab.) As always, this conference is also an excellent place to reconnect with CMP colleagues some that have now known each other for >20 years (I’m not admitting that, however).
In an excellent kick-off presentation, Ann Kelleher, fab manager of Intel’s Fab 11X in New Mexico, reminded us just how large and influential Intel is in the IC world, and discussed the more general issues "do it smaller, faster, cheaper, and greener." Her focus on the "challenges of manufacturing" was not directed specifically to CMP processes, materials, or equipment, but the messages were clearly applicable to all in the audience, and could be viewed as the basic motivation behind nearly all the subsequent work presented.
Kelleher showed how the Intel technology roadmap is sticking to its two-year cycles, even as much of the industry has dropped to three-year cycles for 32nm; this plan uses more complex processes to produce the devices as well as incorporating new materials. (My favorite periodic table chart, originally contributed by Kelin Kuhn, shows the large quantity of elements now in use or evaluation for making ICs — see below). She also showed that Intel is driving to increase the pace of moving technology nodes from R&D to manufacturing, while in parallel rapidly driving yield up the learning curve. (Oh, and of course, continuing to reduce fab cycle time for these more complex chips.)
To meet these challenges, the industry needs materials with consistently excellent quality — no excursions. And, for the unexpected "what we don’t know we don’t know" problems, equipment needs to detect and alert us to these excursions as they happen. In parallel with this quicker-turn, higher performance, and higher yielding manufacturing, Intel is also driving to insure that the materials are not from "conflict" sources and that energy is as "green" as possible (the chipmaker claims to be the largest user of green power in the US). Not specifically mentioned in the presentation, but clearly important in meeting all these challenges, is an understanding of CMP physical structures, mechanisms, and chemistry. All of these topics (as they relate to CMP) were discussed in detail at this 2010 conference.
Karey Holland, Ph.D., managing partner at Techcet Group, has > 25 years of experience in semiconductor technology, including CMP equipment company SpeedFam-IPEC, IBM (where she contributed to interconnect technology development and manufacturing introduction of IBM’s 4Mb DRAM), SEMATECH’s deep-UV lithography Micrascan II project, and Motorola’s microprocessor and memory technology group. Contact: kholland@Techcet.com.