(November 26, 2010) — Di Ma, VP, field technical support at TSMC, gave a presentation at the IEEE Bay Area Nanotechnology Council’s Half-day Symposium (11/16/10, Santa Clara, CA) on technical challenges in 28nm CMOS and beyond. TSMC is trying to determine when to deploy FinFETs; and high-mobility channels (using Ge) are also being investigated.

Listen to Di Ma’s talk: Download or Play Now

Di Ma spoke with Debra Vogler, senior technical editor, ElectroIQ, at the symposium, about silicon interposers, die stacking with through-silicon vias (TSV), and gate-last transistor fab.

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Figure. Packaging and 3D IC trend. SOURCE: TSMC

Ma commented on TSMC’s work with Xilinx on silicon interposers. Going forward, it’s a matter of how large the interposer will be, i.e., whether or not to build different passive devices in the interposer to improve signal integrity, as well as die stacking using TSVs, said Ma (Figure). 

Read about Ma’s gate-last points here.


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