(November 26, 2010) — Di Ma, VP, field technical support at TSMC, gave a presentation at the IEEE Bay Area Nanotechnology Council’s Half-day Symposium (11/16/10, Santa Clara, CA) on technical challenges in 28nm CMOS and beyond. TSMC is trying to determine when to deploy FinFETs; and high-mobility channels (using Ge) are also being investigated.
Figure. Packaging and 3D IC trend. SOURCE: TSMC
Ma commented on TSMC’s work with Xilinx on silicon interposers. Going forward, it’s a matter of how large the interposer will be, i.e., whether or not to build different passive devices in the interposer to improve signal integrity, as well as die stacking using TSVs, said Ma (Figure).