TSMC-work-on-Si-interposers-TSV-die-stacking

(November 26, 2010) — Di Ma, VP, field technical support at TSMC, gave a presentation at the IEEE Bay Area Nanotechnology Council’s Half-day Symposium (11/16/10, Santa Clara, CA) on technical challenges in 28nm CMOS and beyond. TSMC is trying to determine when to deploy FinFETs; and high-mobility channels (using Ge) are also being investigated.

Listen to Di Ma’s talk: Download or Play Now

Di Ma spoke with Debra Vogler, senior technical editor, ElectroIQ, at the symposium, about silicon interposers, die stacking with through-silicon vias (TSV), and gate-last transistor fab.

Click to Enlarge

Figure. Packaging and 3D IC trend. SOURCE: TSMC

Ma commented on TSMC’s work with Xilinx on silicon interposers. Going forward, it’s a matter of how large the interposer will be, i.e., whether or not to build different passive devices in the interposer to improve signal integrity, as well as die stacking using TSVs, said Ma (Figure). 

Read about Ma’s gate-last points here.

POST A COMMENT

Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.

Leave a Reply

Your email address will not be published. Required fields are marked *

NEW PRODUCTS

KLA-Tencor announces new defect inspection systems
07/12/2018KLA-Tencor Corporation announced two new defect inspection products at SEMICON West this week, addressing two key challenges in tool and process monit...
3D-Micromac unveils laser-based high-volume sample preparation solution for semiconductor failure analysis
07/09/2018microPREP 2.0 provides order of magnitude time and cost savings compared to traditional sample...
Leak check semiconductor process chambers quickly and reliably
02/08/2018INFICON,a manufacturer of leak test equipment, introduced the UL3000 Fab leak detector for semiconductor manufacturing maintenance teams t...