by Michael A. Fury, Techcet Group
December 15, 2010 – Following a morning of IEDM keynote talks, the IEEE held a press briefing to give the section chairs an opportunity to highlight what they felt were the most newsworthy talks in their sessions, some of which I chose to attend over the next two and a half days. I can say in retrospect that there was only a moderate correlation between these newsworthy recommendations and talks that were standing room only — the audience clearly knows its way around the dance floor.
During the press briefing, the question was raised about whether or not through-silicon vias (TSV) still qualify as an emerging technology. I thought the response was insightful: when reliability papers begin to appear on a topic, it is no longer an emerging technology. Congratulations, TSV; you are now of legal age. (Be smart, backfill responsibly!)
(Additional information can be found online at 2010 IEDM Technical Program. All figures are reproduced with permission of IEDM.)
5.1: My personal plunge back into device processing began with C.H. Lee of Samsung and a 27nm NAND flash memory with a reported record low 0.00375μm2 unit cell size. VTh distribution is reduced by 50% by using self-aligned reverse patterning in place of self-aligned double patterning, which reduces the bar CD from >10% to <5%. A novel B doping profile gives an initial VTh shift of 500mV with lower leakage. The three-level charge device has a lifetime spec of only 500 cycles, whereas the two-level device is spec’d at 1000-3000 cycles; they will be targeted to different markets.
|Cross-section HRTEM images of the 27nm cell profiles. Active bar CD is 25nm.|
5.2: Presenting to a standing-room-only-crowd, K. Prall at Micron showed joint work with Intel on a 25nm 64Gb MLC NAND with a cell size of 0.0034μm2, which includes 22% overhead. For perspective, the ±5% CD control corresponds to ±3 silicon lattice constants. The STI has a 7:1 AR, and an air gap reduced bit line interference by 25%. At these dimensions, the device uses 30-50 electrons to achieve the state change of 300-500mV. Channel conduction occurs in filaments corresponding to less boron doping; the doping is nominally random but boron clustering does occur.
|Cross-section of the cell in the WL direction showing the WL airgap and reduction in total FG-FG coupling with airgap (red square) and without (blue diamond). WL bending is caused by sample preparation. A 25% reduction in total interference is achieved with the airgap.|
2.3: The stress/strain characteristics of TSV & microbumps in thinned (~10μm) wafers were quantified by M. Murugesan of Tohoku University using μRaman spectroscopy, XPS and I-V curves. CMP was found to give a lower Ra and lower residual stress than ultra poly grinding (UPG), dry polishing (DP), wet etching or plasma etching (PE). CMP residuals were +10MPa to -30MPa, mainly tensile with a periodic distribution. UPG residuals were ~60MPa and DP were ~175MPa, all compressive, indicating that DP is not a suitable stress relief method.
2.4: A novel lock-and-key method for wafer-level 3D integration with tungsten TSVs was presented by K.N. Chen of National Chiao Tung University in collaboration with IBM Research. The lock-and-key structure limits misalignment compared to an oxide recess strategy. The joint resulting from the CuO-CuO bond (400°C for 1hr at 20mTorr under 10kN force) is seamless, with no residual interface visible by TEM. A seal ring around each chip periphery effectively prevents corrosion of the active chip bonds and provides additional mechanical strength to the system.
|Left: Top wafer, Cu key structure, bottom wafer, Cu lock structure.
Right: (a) image of lock-and-key Cu bond structure integrating
2.7μm W TSVs in a 47μm thick Si wafer; (b) no detectable Cu bonding interface of the bond structure.
2.5: Backside chip thinning is being challenged by an extension of the additive "Chipfilm" technology introduced by the Institute for Microelectronics Stuttgart (IMS CHIPS), as presented by E.A. Angelopoulos. Before CMOS processing begins, the wafer is prepared by defining an array of 1μm n+ regions and using anodic etching to make fine over coarse porous silicon in the field between the n+ zones, which do not etch. Hydrogen sintering at 1100°C creates buried cavities in the coarse porosity region. Finally, an epi layer is deposited over the top, which bridges the exposed pore openings. Normal CMOS processing begins on a surface with Ra <7nm and thickness ±0.2μm across the wafer. When CMOS processing is complete, the edge of the chip is etched down to the buried layer and the chip is detached with a pick & place tool that breaks the n+ anchors which remain. Electrical parameters of the "Chipfilm" devices with a total thickness of 18μm or 8μm compare favorably with conventional backside thinned chips. Anchor diameters of 1.4μm and 2μm were also evaluated, but 1μm anchors caused the least damage.
|SEM plan view images of anchor remainders at the backside of detached chips, showing excessive damage for 1.4μm and 2.0μm in contrast to well contained damage for 1.0μm anchors.|
9.6: In a late news paper, Y.Q. Wu of IBM Research described the RF performance of a short (70nm) channel graphene FET on SiC. With careful control to minimize the contact resistance to the graphene, a cutoff frequency of 170GHz was obtained at a drain voltage of 2.2V. With further optimization and use of a self-aligned gate structure, a cutoff of 350GHz is believed to be achievable at 90nm channel length.
|SEM image of a finished RF device (a, b); schematic view of a top-gated RF graphene FET (c).|
8.7: As a former practicing electrochemist, I was compelled to hear J. Go at Purdue explain how he could beat the 59mV/pH Nernst limit with a double-gated FET operating as a DNA biosensor. The trick is to use an ion-sensitive FET with a 20nm silicon body and a backside gate for signal amplification. With a 50nm back oxide, the pH sensitivity of the fluid gate is the expected 59mV. Increasing the back oxide to 200nm increases the fluid gate sensitivity to 240mV/pH. This increase in sensitivity, combined with the appropriate receptors, makes it feasible to develop detectors for cancer biomarker proteins at extremely low levels in the blood.
|Schematic of DGFET-based biosensor. Fluid gate immersed in electrolyte as well as the back gate can control the current in Si body. The receptors to target molecules are immobilized on the top oxide so that the target capture modulates Si electrostatics and shifts the threshold voltage (VT). The screening of biomolecule charge due to the counter ions in electrolyte decreases the magnitude of VT shifts.|
Michael A. Fury, Ph.D, is senior technology analyst at Techcet Group, LLC, P.O. Box 29, Del Mar, CA 92014; e-mail email@example.com.