ASMC 2011: Approaching device scaling, manufacturing challenges with partnerships

by John Behnke, VP of worldwide sales and marketing, Intermolecular Inc.

May 18, 2011 – Another eventful (but still rainy) day at the SEMI/IEEE Advanced Semiconductor Manufacturing Conference (May 16-18), bookended by the two highlights: an information-rich and wide-ranging keynote talk by Gary Patton, VP of the semiconductor R&D center in IBM’s systems and technology group, and a panel discussion on "Models for successful partnerships in semiconductor manufacturing." (Before getting into those, Monday evening’s poster session was quite good, with lots of productive interaction; it brought out the international composition of the attendees, with Europe and Asia well-represented. Plenty of good posters were on display; it was difficult to pick the best one, and there will likely be several in close competition for the award.)

Patton’s keynote was remarkable for both scope and depth: he incorporated an unbelievable amount of high-level industry perspective and technical depth into less than an hour. He noted that there are now something like a trillion devices connected to the Internet, with 2 billion people online and some 4 billion using mobile devices generating 225,000 terabytes of data a month. Teenagers send an average of 100 text messages per day, he added — this actually seems low, based on what I see my daughters doing.

On the technology side, Patton noted that device scaling, which had traditionally provided intrinsic improved performance, now requires significant device engineering to overcome the "pitch hole" that degrades performance with scaling. This is forcing new material use and is one of the many things driving R&D costs up.

Another challenge is 3D packaging, where trends at the wafer level and package level are challenging reliability. On the one hand, ultralow-k porous films being used in wafer-level interconnects make it more difficult to maintain a rigid substrate; on the other hand, new lead-free solder bumping requirements are more rigid and less deformable than their predecessors. The upshot is that 3D packaging schemes must deal with internal stresses that can cause interconnect failures.

ASMC 2011
Day 1: Rain doesn’t damper the spirit
Day 2: Approaching device scaling, manufacturing challenges with partnerships
Day 3: EUV, image sensors, and a capital perspective

Picking up a theme from Norm Armour’s first-day keynote, Patton cited a number of successful collaborations that IBM has managed, in part because of a 4× increase in R&D costs over the last decade. Referring to technology development as an "ecosystem," he cited successes working with ASML, Toppan Photomasks, Zeiss, and Mentor Graphics on the critical source-mask optimization (SMO) technology that is allowing optical lithography to extend to 20nm-14nm, and with ATMI on high-dose implant strip.

Like Armour, Patton was optimistic about EUV litho technology, predicting it would come into early use at the 14nm node, and then more extensively at 11nm.

The panel discussion, ably moderated by veteran journalist Dave Lammers, featured four perspectives on how partnerships can be applied to chipmaking challenges.

Walid Ali, senior manager for R&D at the Abu Dhabi-based Advanced Technology Investment Company (ATIC), gave a global perspective on the human capital needed for development of new chipmaking centers, noting that there are some areas of concentrated activity but others (like Brazil) where there are many engineers but little silicon presence. Abu Dhabi is drawing on its large expat community, including many engineers from the Indian subcontinent, to fill out its expanding tech sector; he called out academic institutions and other educational efforts in their plan to help build the ranks of engineers. In response to a question from Lammers, Ali also hinted that the ATIC-funded fab in Abu Dhabi will be watching some disruptive technology introductions, but wouldn’t divulge details.

The panel’s academic representative, Mike Fancher of the New York State Center for Advanced Technology in Nanoelectronics, and associate professor of Nanoeconomics, at the SUNY College of Nanoscale Science and Engineering (CNSE), noted that the Albany-based effort has been working in that area in its 800,000-square-foot facility. He noted that some 12,000 jobs have been created or retained in the region by the program since 2001, with over 250 participating industry partners.

Another hub of industry-academic collaboration is CEA-Leti, the French research center, where over 4000 people work side-by-side, including ~1500 students, ~1600 researchers, and ~900 industry assignees. The presentation by equipment asset manager Olivier Demolliens made me want to visit, and not just because of the skiing opportunities in the Grenoble area — successful joint-development programs have included double-patterning work with Nikon, multibeam lithography development with Mapper, and an interesting effort in directed self-assembly with an unnamed partner.

Also on the panel was Ari Komeran, Intel industry development manager/director of Europe, the Middle East, and Africa. While Intel has something of a reputation for being self-reliant, it also has a tremendous number of partnerships and collaborations with universities, startups, and suppliers. He highlighted the Israeli model of providing government and academic support for startups as a good alternative to the venture capital model, providing good financial leverage.

An audience question touched on the problem of financing education. Fancher noted that students at the College of Nanoscale Science and Engineering are all on fellowships and get graduate student wages. Demolliens added that in France, students don’t have to pay, but that it’s challenging to attract them to tech careers. "We have to get people to dream," he said.

Next report will include a tour of the Luther Forest Technology Campus, where GlobalFoundries’ Fab 8 is located, and final ASMC 2011 wrap-up.

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