July 26, 2011 — 3D semiconductor packaging processes involve various groups, and standards are important in the hand-offs between them, explains Mark Berry, sales director at Metryx. He covers how to use metrology to protect wafer yields in 3D packaging.
Berry spoke to ElectroIQ in a podcast interview at SEMICON West 2011 this month in San Francisco, CA.
"People who are receiving wafers need something they can benchmark," said Berry. Towards the end of the through silicon via (TSV) process, "if you take too much silicon off the wafer, you going to take the dies with it…and if you take too much silicon off the wafer, you’ll expose the circuitry." Metrology has to play a role in controlling wafer processing to achieve yields that make 3D ICs cost-competitive, he said.
Another concern with 3D semiconductors is that the end user already has placed a lot of value in the wafers by the time TSVs are formed, noted Berry. Because the transistors have already been made, if the relatively simple and inexpensive 3D packaging process fails, then end users are writing off a lot of product. "But you don’t want to spend a lot of money in putting the metrology into place to get it right," so the key thing is "a balance between managing the process, understanding how the process flows, measuring at the right points so you know where the failure events will be so you can select them and control them, but not overdoing the metrology," Berry concludes.