Present on interposer technology

September 20, 2011 — The first annual Global Interposer Technology Workshop (GIT 2011) will take place November 14-15 at Georgia Institute of Technology (GA Tech), convening industry experts, global academic researchers, and student leaders to share interposer technology research, development, applications, markets and manufacturing infrastructure.

Interposers are used to create "More than Moore" 3D or 2.5D semiconductor packaging.

To present at the conference, submit a title for consideration (presentation or poster) by October 2 at Selected submitters will be notified by October 15.

Technical sessions will cover electrical and mechanical design, silicon and glass interposers, chip- and board-level interconnect, interposer applications and markets, and the manufacturing infrastructure for these technologies.

The plenary keynote lineup is as follows:

  • Subramanian Iyer, IBM – "Silicon Inteposers: The First Step Towards Three Dimensional Integration"
  • Doug C.H. Yu, TSMC – "Semiconductor Paradigm Shift and the Advantages of Foundry Integration"
  • Suresh Ramalingam, Xilinx – "Stacked Silicon Intereconnet: Road to Production"
  • Jerome Baron, Yole – "Interposer markets and Applications"
  • Rao Tummala, Georgia Tech – "3D Packaging Perspective at Georgia Tech 3D ICs vs 3D Interposer"

The event will feature posters presented by students along with the industry, research, and academia speakers.

GIT 2011 is sponsored by IEEE, CPMT, IMAP, iNEMI, and SEMI. Learn more at

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