October 11, 2011 – PRNewswire — EV Group (EVG) and All Silicon System Integration Dresden (ASSID) of Fraunhofer IZM will jointly develop high-volume 3D IC manufacturing processes, focusing on temporary bonding and debonding processes to support chip-to-wafer bonding with up to 600um-thick topographies.
ASSID will host the collaboration with its 300mm 3D manufacturing/packaging line in Dresden, using EVG850 TB/DB systems already installed there. The partners will also use ASSID test samples and demonstrator materials. EVG will contribute 3D IC fab tool and process expertise. ASSID’s established network with other research institutes and universities can be used to verify viability of new developments.
Chip-to-wafer bonding allows manufacturers to test die prior to 3D bonding, resolving low-yield wastage associated with bad die. Also, heterogeneous technologies (different sizes, feature dimensions, etc.) can be bonded in 3D die stacks with a broad range of functionality (logic, memory, mixed signal, photonics, etc.) in a compact form factor.
Today’s advanced temporary bonding/debonding processes support bonded wafer topographies up to 100um thick. More complex die structures require thicker wafers. EVG and ASSID will work on improving rigid backgrinding support during wafer thinning and low-vertical-force debonding to avoid defects during debonding.
ASSID also announced today that it has installed an Altatech Semiconductor 300mm CVD system for advanced TSV fab.
Fraunhofer IZM-ASSID is tasked with developing 3D packaging technologies, including new interconnect and assembly processes. As part of the Fraunhofer IZM Institute, which specializes in transferring IC advanced packaging and system integration research results to industry, ASSID is integrated into a technology network of applied research institutes and universities.
EV Group (EVG) makes wafer-processing tools for semiconductor, MEMS and nanotechnology applications. More information is available at www.EVGroup.com.