STATS ChipPAC brings FOWLP to stacked packages for <1mm profile

March 6, 2012 — Semiconductor test and advanced packaging service provider STATS ChipPAC Ltd. (SGX-ST:STATSChP) uncrated its next-generation 3D embedded wafer-level ball grid array (eWLB) package-on-package (PoP) technology, with a package profile height below 1.0mm.

The PoP format aims for higher thermal and electrical performance, increased bandwidth and speed in an ultra thin package profile, with design flexibility in integrating memory and logic semiconductors. Industry standard is 1.4mm total stacked package height, 30% more than STATS ChipPAC’s new 3D eWLB. STATS uses fan-out wafer level packaging (FOWLP) to reduce the bottom PoP package height below 0.5mm. The technology also offers tighter substrate line/space capability. eWLB PoP is available in single or double-sided configurations.

STATS ChipPAC also offers a co-design process with packaging customers to optimize the functional performance of the ultra thin 3D package. The 3D PoP form factor targets advanced mobile applications: smartphones, media tablets, cloud computing, etc. Microprocessors are adopting the technology. Computing-sector customers are also using eWLB to reduce substrate complexity and cost.

Over 200 million eWLB units are in the market, with package architectures including small die, large die, multi-die and multi-layer designs.

STATS ChipPAC will present on innovative 3D packaging, covering eWLB, low-cost copper (Cu) column flip chip PoP technology, and stacked die integration of RF packages at the IMAPS International Conference and Exhibition on Device Packaging this week in Scottsdale, AZ.

STATS ChipPAC Ltd. provides semiconductor packaging design, assembly, test and distribution services. STATS ChipPAC is listed on the SGX-ST. Further information is available at

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