SEMATECH highlights from VLSI-TSA

April 26, 2012 — SEMATECH experts reported on innovative processes for advanced CMOS logic and memory device technologies and 3D through-silicon via (TSV) manufacturing at the International VLSI Technology, System and Applications Symposium (VLSI-TSA) on April 23-25, 2012.

SEMATECH’s international researchers reported on innovative materials and transistor structures to address performance, power, and cost. Research covers high-k/metal gate (HKMG) materials, resistive RAM (RRAM) memory, and planar and non-planar CMOS technologies.

A direct metal bonding interconnect approach for 2.5D and 3D integration was introduced by Sitaram Arkalgud, director of SEMATECH’s 3D interconnect program. Arkalgud revealed SEMATECH’s copper-to-copper direct bonding (CuDB) technology that can scale chip-to-chip interconnects beyond what solder can achieve in mechanical, electrical, thermal, and reliability performance. He also discussed recent progress and remaining technical and economic hurdles in moving toward high-volume manufacturing of CuDB interconnects.

SEMATECH technologists also reported technical advances in the following areas:

Silicon Channel Devices: Evaluating stress-induced leakage current (SILC) in full gate-last (FGL) HKMG devices to address sources of SILC and propose possible process options for improvement. A high quality interlayer during gate stack formation was found to be critical to improving FGL device performance and reliability.

Silicon Channel Devices: Modeling positive bias temperature instability (PBTI) degradation in Zr-doped HfO2 gate stacks by considering fast and slow electron trapping processes. PBTI was found to improve when the fast trapping component was suppressed.

Non-Silicon Channel Devices: Using different ALD oxidizers to study the effects of III-V oxides on device performance. With a O3 precursor, As-As, AsOx, GaO, and In2O3 were found to be the main native oxides/byproducts. H2O-based precursors remain stable with no III-V oxide detected throughout a low temperature flow. Electrical performance also improved with H2O-based high-k, suggesting that H2O-based ALD is the key process for III-V CMOS.

Non-Silicon Channel Devices: Exploring alternative high-k gate dielectrics for III-V, Ge and Si MOSFETs. High-field carrier mobility and MOSFET parameter characteristics were improved by atomic layer deposition (ALD) of a thin beryllium oxide layer to passivate the interface between the Si channel and high-k gate dielectric.

Non-Planar Devices: Studying FinFET Vt tuning. Both performance and the electrical properties of the gate stack were improved by an Al implantation, representing progress towards realizing multi threshold voltage FinFET device architectures for the 14 nm node and beyond.

Non-Planar Devices: Studying the impact of fin doping on high-k/midgap metal gate SOI FinFETs. Threshold voltage can be effectively modulated with doping in ~25 nm wide fins. For sub-10 nm fin widths, however, the active dopant atoms must be precisely placed inside the fins, which ion implantation cannot do. A conformal doping technique with perfect dose control, such as monolayer doping, was discussed which may be the solution for future planar and non-planar devices.

Non-Planar Devices: Evaluating the parasitic capacitance of planar FETs and double-gated (DG) FinFETs. Optimization with a fixed fin-to-height ratio significantly reduces parasitic capacitance, which renders DG FinFETs comparable to planar FETs. Fin width and height must be controlled in the DG FinFETs, otherwise the parasitic capacitance uniformity will degrade.

Non-Planar Devices: Investigating the impact of source/drain (S/D) activation anneal on GAA pFETs. Low temperature pFETs were fabricated and benchmarked against devices with a S/D activation anneal. When S/D is implanted before the gate spacer, the un-annealed devices exhibited higher peak transconductance and drain current but have a higher off-current than their annealed counterparts. Pre- and post-spacer S/D implant schemes were also explored.

Advanced Non-Volatile Memory: RRAM switching performance up to 1×108 cycles at low power and a 100x reduction of the high-resistance-state current was achieved by identification and utilization of key parameters for establishing superior control of the RRAM conductive filament formation.

The International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) is sponsored by Taiwan’s Industrial Technology Research Institute (ITRI) in association with Institute of Electrical and Electronics Engineers, or IEEE, a leading professional association for the advancement of technology. VLSI-TSA is one of many industry forums SEMATECH uses to collaborate with scientists and engineers from corporations, universities and other research institutions, many of whom are research partners.

SEMATECH’s front end processes program, located at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany, is exploring innovative materials, new transistor structures, and alternative non-volatile memories to address key aspects of system-level performance, power, variability, and cost and to help accelerate innovation in the continued scaling of logic and memory applications. SEMATECH is an international consortium of leading semiconductor device, equipment, and materials manufacturers. Learn more at this year celebrates 25 years of excellence in accelerating the commercialization of technology innovations into manufacturing solutions. Through our unwavering commitment to foster collaboration across the nanoelectronics industry, we help our members and partners address critical industry transitions, drive technical consensus, pull research into the industry mainstream, improve manufacturing productivity, and reduce risk and time to market. Information about SEMATECH can be found at www.sematech.org.

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