For almost five decades, performance improvements and cost reduction of ICs have been cornerstones of the growth of the semiconductor industry. All these years, the semiconductor industry continued to scale down transistor dimensions, and, at the same time, maintained its historical 30 percent cost saving per logic gate, node after node.
Today, the question we are all concerned about is: can the industry keep up this trend? I fully expect that the technical roadmap for scaling, backed up by the ITRS roadmap, will continue for at least one decade. At the same time, the costs associated with such a further node progression will increase significantly. Equipment and R&D costs keep rising node after node, and continuous investments in fabs and equipment remain crucial if the industry wants to stay at the forefront of innovation. This may push the industry towards a new round of consolidation. Just as was the case with IC companies in the past, a consolidation of equipment suppliers could be a necessity to cope with the rising costs.
So the real question is: can the industry upgrade the IC performance and maintain its 30 percent cost saving for integrated circuits at the same time? The answer is not straightforward. It will depend, among others, on the complexity of the technologies and equipment we’ll need. One notable example, is of course, EUV. As EUV relaxes the need of multiple patterning, it would significantly reduce the processing cost per wafer. On the other hand, additional investment costs will come along with introducing EUV tools in the fab. Another worry is wafer size. Historically, the semiconductor industry used wafer scale-up as an additional means to maintain the cost reduction per transistor. But will it be advantageous this time to scale up towards 450mm wafers? In the coming years, industry leaders must make smart choices on breakthrough technologies and wafer size. More than ever, these decisions will be driven by economics.
The same trends that dominate the semiconductor industry can be witnessed at the R&D level as well. At imec, we perform CMOS R&D two generations ahead of industrial needs. 30 years ago, our initial focus was on the 1.25µm node. In 2014 our workhorse is the 7nm node and beyond. To print these extremely small features at an affordable price, we need the accuracy and “simplicity” of EUV lithography. Also, in answer to rising equipment costs, we need to further strengthen our collaboration with leading equipment and material suppliers of the IC industry, which more than ever will play a key role in our innovation hub. We believe this will reinforce the interaction between IC manufacturers and suppliers, and is essential for implementing the next steps in innovation and scaling.
2014 and 2015 will be crucial years. The industry will introduce and ramp up the 14nm technology node and use advanced FinFETs in an industrial processing technology. We will witness shortly the real cost of this advanced technology node, allowing us to learn for the future. At first, EUV will be part of a future technology. If its throughput can be improved and the tool becomes mature, it will gradually be introduced in the years to come and will create additional operational cost benefits compared to immersion lithography. For sure, 2014 will be an exciting year.