InGaAs is a promising channel material for high-performance, ultra low-power n-MOSFETs because of its high electron mobility, but multiple-gate architectures are required to make the most of it, because multiple gates offer better control of electrostatics. In addition, it is difficult to integrate highly crystalline InGaAs with silicon, so having multiple gates offers the opportunity to take advantage of the optimum crystal facet of the material for integration.
Transistors with high mobility channels will likely be required for the 10nm and 7nm device generations, scheduled to go into production in 2016/2016 and 2017/2018, respectively. InGaAs is a good candidate for NFETS, while germanium is the candidate of choice for PFET devices.
At the upcoming International Electron Devices Meeting (IEDM), to be held December 8-11 in Washington, D.C., a research team led by Japan’s AIST will describe how they built triangular InGaAs-on-insulator n-MOSFETs with smooth side surfaces along the <111>B crystal facet and with bottom widths as narrow as 30nm, using a metalorganic vapor phase epitaxy (MOVPE) growth technique. The devices demonstrated a high on-current of 930 µA/µm at a 300nm gate length, showing they have great potential.
The National Institute of Advanced Industrial Science and Technology (AIST) is a public research institution largely funded by the Japanese government. About 2300 researchers (about 2050 with tenure: about 80 from abroad) and a few thousands of visiting scientists, post-doctoral fellows, and students from home and abroad are working at AIST. About 650 permanent administrative personnel and many temporary staff support research works of AIST.