BOBBY ISAACS and ANYA CORNELL, Texas Instruments, Dallas, Tex.
Results can depend on the properties of the wafers used, the conditions of the implant, the conditions of the anneal process, and even the measurement technique.
Semiconductor chip geometries continue to shrink, causing once unimportant parameters in the manufacturing process to become more critical. With the shrinkage in transistor size and requirements for improved precision in devices, ion implantation has become an increasingly more delicate and accurate operation. Implantation angle has become extremely important as transistors have decreased in size and voltage specifications. Adjustment and pocket implants, channeling implants, and high accuracy sidewall and HALO implants have become requirements for high performance, with little to no tolerance for incorrect implantation placement.
|FIGURE 1. Illustration of wafer slicing angle and associated offset.|
Older generations of ion implanters have been designed with only cursory regard to the extreme precision now required for implant placement. Because of this, semiconductor manufacturers must regularly monitor the implantation angle of these tools as part of normal production operations. In this monitoring, multiple potential issues exist that could cause a misinterpretation of the proper implantation angle, resulting in faulty tool calibration or production of out of tolerance product. This article will describe several variables to be considered when defining the angle of implant for a tool, and offer recommended conditions to achieve reliable and repeatable performance on two older implant tool sets.
The standard production test to determine if the angle of implant is accurate involves implanting 5 to 7 wafers tilted around a theoretical channeling angle, annealing the wafers to activate the implant, and charting the sheet resistance vs. implanted angle to find the channel. This procedure is commonly called a V-curve test. The as-measured channeling angle (found by identifying the minimum sheet resistance of the charted curve for the wafers, or the bottom of the “V”) should be equal to the theoretical channeling angle if the tool set-up is accurate. Unfortunately, the number of steps required by this procedure introduces errors that could lead to a false result. The properties of the wafers used, the conditions of the implant, the conditions of the anneal process, and even the measurement technique can all significantly affect the outcome.
One of the most commonly overlooked variables that can introduce significant error into measurement of the angle of implant is the wafer which is used for the testing. One relevant silicon property of the wafers, the surface orientation angle offset (angle tolerance of the on-axis cut), has a significant effect. All wafers have a base surface orientation angle offset, as required by the process of slicing the wafers from the ingot (FIGURE 1).
This offset can directly translate into an offset in the V-curve measurement, depending on the angular rotation of the slice. It has been shown in previous work that channeling is minimized at implant angles higher than 0.5°. In this work, the effect of the orientation angle offset on channeling was similarly studied. Implants were performed with 200mm, , N-type (phosphorus-doped) CZ wafers of resistivity 3-5 Ω-cm, surface orientation angle of 0.0+/-1°(on-axis ), Oi spec of <=32 ppma (ASTM-79), and LLS of <20 @0.20µm. The wafer type was chosen for use with Boron implant (P-type dopant) and the orientation was picked for its good channeling properties. Using the above specification, wafers were chosen at various extremes of the angle window (close to 0° and close to 1°) in order to characterize the effect of wafer angle variation. Other silicon properties shown in the spec above, such as surface defects, oxygen concentration, and resistivity are in the standard range for a typical test wafer. These parameters have a lesser effect on the implant angle measurement and were not explored in this study.
|FIGURE 2(L). Comparison of Varian E500 V-curves generated using Thermawave vs TRS-100. FIGURE 3(R). Effect of wafer orientation angle offset on V-curve of Axcelis Optima MD.|
The two implant tool types used were an Axcelis Optima MD implanter and a Varian E500 implanter. Implant conditions were chosen as follows based on experimentation and comparison of common processes among multiple manufacturing facilities utilizing several tool types: Boron11 at 100 keV energy, 1.0e14 ion/sq dose, 35° tilt, and 0° twist. Boron11 was chosen as the dopant for its small mass and channeling properties, as discussed in Downey, et.al. Energy of 100 keV is high enough to prevent outgassing of the dopant during the anneal process, and 1.0e14 ion/sq dose was chosen to place the resultant resistance as measured on a standard Tencor RS-100 into a stable range for the measurement equipment. For all tests, the ion beam was optimally tuned to minimize beam instability or non-linearity. The potential process variables influencing beam steering on the tool were not explored during this experimentation, but it should be commented that an improperly tuned ion beam will also significantly affect the result. A tilt angle of 35° was chosen as the optimal channeling condition. Although multiple potential channeling angles exist for  N-type silicon wafers, the angle of 35.26o has shown the most sensitive, clear channel for implant angle testing, and it is also recommended by Varian Semiconductor. A twist angle of 0° was applied for best resolution of the channel in all but one of the tests, which utilized a rotation angle of 90° to characterize the effect of the wafer substrate angle offset.
The anneal process needed to be selected in such a way as to eliminate any variation or sensitivity due to temperature of anneal, anneal time, or even annealer tool type. An anneal temperature of 1060oC for 30 seconds was selected from earlier work as the condition at which small temperature variations can be tolerated. Two types of annealer tools were used – an Axcelis Summit furnace annealer, and an AG Associates 8800 lamp annealer – to determine if the V-curve could be shifted through anneal by varying the tool type.
|FIGURE 4. Effect of wafer orientation angle offset and wafer rotation on V-curve of Varian E500|
Measurement of sheet resistance is well documented for ion implant processing. For this experimentation, Thermawave and Tencor RS-100 measurement tools were researched to identify possible areas of concern in the measurement of V-curve wafers. The advantage to Thermawave processing is the elimination of the need for anneal after implant, removing this source of potential variation. Also, a previous experiment with a different implant has shown that the Tencor RS-100 produces a sharper V-curve than the Thermawave (see sample V-curve in FIGURE 2). Therefore, the Tencor RS-100 tool was chosen for the present work. Testing on the Tencor RS-100 was performed using both 9-point and 49-point radial measurement patterns.
Results and discussion
By far the strongest effect was observed from the silicon wafer orientation angle offset. In particular, at angles above 0.5o, the effect was so pronounced that it shifted the V-curve. See below graph of two sets of wafers processed with identical implant and anneal conditions. The only difference was the orientation angle offset (0.04° vs 0.68°), as shown in FIGURE 3.
In an effort to further characterize the effect of a larger orientation angle offset of the wafers, testing was performed by rotating the wafers 90o during the implant to measure the change in the resultant V-curve. Using wafers with very small surface orientation offset angles (0.04o), the change in the measured V-curve could not be easily seen. However, using wafers with a surface orientation offset angle above 0.5o (0.68o), the change in the measured rotated V-curve became much more visible (FIGURE 4). Repeatability of the tests using high surface orientation angles was also noted to be inconsistent, with significant variance in results from test to test.
|FIGURE 5. Effect of anneal tool and temperature on V-Curve of Varian E500.|
Based on the results presented above, it is our recommendation that high-angle offset wafers (above 0.5°) should not be used for implant angle qualifications. It is also recommended that the surface orientation angle of the test wafers be scrutinized if the V-curve produced shows abnormal variance from the expected outcome. To reduce variability from other wafer parameters, we also recommend a tight resistivity specification (ex: 3-5 ohm-cm) for the silicon ingot, and advocate the use of wafers not only from the same ingot, but from the same area of the ingot, to ensure similar properties.
Minor effects were observed from other variables studied. An experiment comparing two anneal temperatures confirmed earlier findings1 of 1060C being the optimal temperature to produce a sharper V-curve (FIGURE 5). The type of anneal tool was also a factor. Although the process was matched as closely as possible through matching of the thermal budget, a difference could be seen between the annealer types (Fig. 5, left). Based on the clarity of the V-curve inflection on the lamp annealer, this tool was used as the benchmark for anneals during other experiments.
|FIGURE 6. Effect of measurement map resolution on V-Curve of Axcelis Optima MD.|
As for the Sheet Resistance measurement, very little to no effect was observed from varying the measurement pattern and number of measured points. A 9-point measurement showed the same accuracy as a 49-point measurement, making the additional points unnecessary (FIGURE 6).
As a result of this testing, multiple recommendations can be made to ensure accurate and repeatable measurement of the implant angle of a tool. These areas can result in significant variation of results if not accounted for during testing. The silicon quality of the wafers is one of the most overlooked variables in performance of implant angle measurement. The surface orientation angle offset can significantly change the measured implant angle, especially in ranges above 0.5° (from on-axis cut). Wafers with angle cut tolerance greater than 0.5° produce inconsistent results, severe enough to shift the sheet resistance values or even the entire V-curve, and are therefore not recommended for implant angle testing.
The parameters used in implantation also contribute significantly to the resolution and accuracy of a V-curve test. Although multiple potential channeling angles exist for  N-type silicon wafers, a 35° angle is recommended as the most sensitive, clear channel for implant angle testing.[1,4] The implanted species, energy, and dose all contribute to the stability and repeatability of the measurements. Once implanted, the anneal of the wafer must be tuned to a temperature and thermal budget that minimizes variation, as this will also cause slight changes in results. Finally, measurement techniques can change the outcome of a V-curve test through differences in the measurement tool used.
Once the angle of implant of a given tool is characterized, regular verification (qualification) is highly recommended, especially for events which involve components handling wafer orientation. To save on wafer cost, a test may be performed using 1 or 3 wafers once the baseline sheet resistance of the channeling angle is obtained, and charted through standard SPC techniques. If a failure is observed, escalation of the testing can then include a full 5 or 7 wafer V-curve test to determine if the angle of implant has shifted. Standard troubleshooting for common sheet resistance failure events should be included in disposition of a failure, since hardware issues in the form of leaks, contamination and other failure modes can influence the sheet resistance measurement obtained during angle testing.
The authors would like to thank TI silicon material technologist Thomas McKenna for valuable insight into starting material properties, as well as Jeff Bell of SUMCO-USA for providing substrate orientation angle data.
1. Rathmell, M.A. (2006). Implant Angle Monitoring – A Comparison of Channeling Features. Ion Implantation Technology Conference Proceedings, Marseille, France, June 11-16.
2. Downey, D.F., Arevalo, E.A., Eddy, R.J. (2000). The Significance of Controlling “Off-Axis” (from 1-0-0) Oriented Si Wafers During High Angle Implants. Ion Implantation Technology Conference Proceedings, Alpbach, Austria, September 17-22.
3.Guo, B.N., Variam, N., Jeong, U., Mehta, S., Posselt, M., & Lebedev, A. (2002). Experimental and Simulation Studies of the Channeling Phenomena for High Energy Implantation. Ion Implantation Technology Conference Proceedings, Taos, New Mexico, USA, September 22-27.
4.Canning, Stephen, (7/17/2006). BKM – System related Checks for Process Control, PSB2621A, Varian Semiconductor VSEA Product Support Bulletins, Pg. 6.
BOBBY ISAACS is an Ion Implant Fabrication Engineer for Texas Instruments’ DMOS5 manufacturing site in Dallas, TX (email@example.com). ANYA CORNELL is an Ion Implant and Silicon Processing Engineer for Texas Instruments’ MFAB manufacturing site in Portland, Maine.(firstname.lastname@example.org).