Altera Corporation and TSMC today announced the two companies have worked together to bring TSMC’s patented, fine-pitch copper bump-based packaging technology to Altera’s 20 nm Arria 10 FPGAs and SoCs. Altera is the first company to adopt this technology in commercial production to deliver improved quality, reliability and performance to Altera’s 20nm device family.
“TSMC has provided a very advanced and robust integrated package solution for our Arria 10 devices, the highest-density monolithic 20nm FPGA die in the industry,” said Bill Mazotti, vice president of worldwide operations and engineering at Altera. “Leveraging this technology is a great complement to Arria 10 FPGAs and SoCs and helps us address the packaging challenges at the 20nm node.”
TSMC’s leading-edge flip chip BGA package technology provides Arria 10 devices with better quality and reliability than standard copper bumping solutions through the use of fine-pitch copper bumps. The technology is able to accommodate very high bump counts as required by high-performance FPGA products. It also provides excellent bump joint fatigue life, improved performance in electro-migration current and low stress on the ELK (Extra Low-K) layers, all highly critical features for products employing advanced silicon technologies.
“TSMC’s copper bump-based package technology provides excellent value for small bump pitch (<150um) advanced silicon products featuring ELK,” said David Keller, senior vice president, business management, TSMC North America. “We are pleased that Altera is adopting this highly integrated packaging technology.”
Altera is shipping Arria 10 FPGAs based on TSMC 20SoC process technology and featuring this innovative packaging technology. Arria 10 FPGAs and SoCs provide the FPGA industry’s highest density in a single monolithic die and up to 40 percent lower power than the previous 28nm Arria family.
TSMC’s copper bump-based package technology is scalable and ideal for products that feature large die size and small bump pitch. It includes a DFM/DFR implementation from TSMC that adjusts package design and structure for wider assembly process windows and higher reliability. The technology has demonstrated better than 99.8 percent production-level assembly yields.