Kandou introduces in-package chip interconnect enabling lower cost semiconductor solutions

Kandou Bus has announced the Glasswing family of chip interconnects targeted for in-package chip-to-chip links. Kandou introduced Chord Signaling in February 2014 and outlined how signals can be correlated across more than two wires to achieve higher bandwidth and lower power with excellent signal integrity and low latency. The Glasswing architecture optimizes Chord Signaling to address the unique challenges of both substrate and interposer in-package solutions.

For the first time in history, the cost to manufacture a transitor in the most advanced silicon process has increased compared to the previous generation. As a result, system architects are looking for more cost effective ways to partition and package silicon devices for optimal performance. Integrating several chips into a shared package can be attractive, but only if the in-package communication between chips allows for extremely high bandwidth and very low power.

“Architectures that combine multiple chips into a single package are not new,” said Kandou Founder and CEO Amin Shokrollahi, “but increasing bandwidth and improving signal integrity while maintaining very low power in an affordable package is a daunting task. Glasswing delivers on the promise of 2.5D integration by providing a cost-effective solution that offers unprecendented, in-package, chip-to-chip bandwidth at very low power.”

Glasswing Architecture and Applications

The core of Kandou’s Glasswing technology is a chordal code that delivers five bits over six correlated wires within each clock cycle. Through a simple yet elegant comparator network, signals are received and translated into bits resulting in much higher overall link throughput.

Depending on the application the link can run at up to 25 GBaud and deliver up to 20.8 Gbps per wire at less than 0.5pJ/bit in a 28nm logic process. These benefits are ideal for very short links (less than 10mm) such as the connnection inside a package between a DRAM stack and a controller, the link to an out-boarded high speed SerDes, or the coherency buses of a partitioned multi-core processor. The link can also work over channels up to 25mm in length with slightly more power.

To fully realize the benefits of the Glasswing architecture, Kandou has developed optimized circuits and architectures for all parts of the transmission chain including serializers, drivers, receivers, CDR units, skew mitigators, equalizers, deserializers and test circuits.

Kandou’s Glasswing product development is underway for the first instantiation of the PHY optimized for in-package links between processor cores. A comprehensive 28nm PHY evaluation package will be available Q3 2015.

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