ON Semiconductor demonstrates high efficiency 3D sensor stacking technology

ON Semiconductor has successfully characterized and demonstrated its first fully-functional stacked CMOS imaging sensor featuring a smaller die footprint, higher pixel performance and better power consumption compared to traditional monolithic non-stacked designs. The technology has been successfully implemented and characterized on a test chip with 1.1-micron (µm) pixels and will be introduced in a product later this year.

Conventional sensor designs in a monolithic substrate process require separate die area to support both the pixel array and supporting circuitry. With 3D stacking technology, the pixel array and the supporting circuitry are manufactured on separate substrates and then stacked with connections between the two made with through silicon vias (TSVs). This allows the pixel array to overlay the underlying circuitry and result in a more efficient die floorplan. With this approach, design engineers can optimize each part of the sensor for imaging performance, cost, power and die size. With the optimization of the pixel array, sensors can have improved pixel performance with lower noise levels and enhanced pixel response. The underlying circuitry can use more aggressive design rules to lower power consumption as well. The smaller overall footprint supports today’s advanced camera modules that integrate Optical Image Stabilization (OIS) and additional data storage in the same module footprint.

3D stacking technology is an exciting breakthrough that enhances our ability to optimize ON Semiconductor’s future sensors,” said Sandor Barna, vice president of Technology for ON Semiconductor’s Image Sensor Group. “This technology provides manufacturing and design flexibility to ensure continued performance leadership across our entire sensor product portfolio.”

ON Semiconductor will be demonstrating its latest image sensor technology and products at CES 2015 in Las Vegas from Jan. 6-8.

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