Keynote panel: Challenges abound for sub-14nm

By Pete Singer, Editor-in-Chief

SEMICON West 2015 kicked off Tuesday morning with a keynote panel session that addressed the challenges of “Scaling the Walls of Sub-14nm Manufacturing.” The general consensus was that future progress is dependent on better coordination and collaboration between design, manufacturing and packaging companies and people.

The panel consisted of Jo de Boeck, Senior Vice President, Corporate Technology at imec, who acted as the moderator; Gary Patton, Chief Technology Officer and Head of Worldwide Research and Development at GLOBALFOUNDRIES; Michael Campbell, Senior VP Engineering at Qualcomm; Calvin Cheung, Vice President, Business Development and Engineering at ASE and Subhasish Mitra, Associate Professor, Dept. of EE and CD at Stanford University.

Tuesday panel

Patton said the end of scaling was nowhere in sight. “People have talked about the end of scaling. Scaling is not going to end. I am not worried about solving the physics challenges,” he said. “We have run into many barriers over the years and we always find a way to get around it.

Patton said what worries him is doing it in a way “that can deliver to our customers a real value proposition for going to that next technology node. The cost of doing design in these nodes is increasing at a pretty rapid rate and we have to provide them with a return on investment. It’s becoming more challenging,” he said.

He noted that in the past most breakthroughs, such as high-k metal gates, took over 10 years in the research stage before they were ready for manufacturing. That was one reason behind the merger between IBM and GLOBALFOUNDRIES: access to 16,000 some IBM patents. Patton also mentioned IBM’s expertise in a ASICs business, differentiated IP, RF technology – both silicon germanium as well as RFSOI – as well as 3D and 2.5D technologies.

Qualcomm’s Mike Campbell said the biggest threat to Moore’s Law is yield. “Yield is now an end-to-end question,” he said. “That doesn’t just mean semiconductor yield today. It’s the package yield on top of that and then the systems yield.”

Campbell said he’d like to see that end-to-end yield contained in a productivity model. “If you have a 10nm or 7nm silicon piece and it works to the spec at the silicon level, but then we change the stress characteristics because we have to saw and dice it up into a package. Then we put it into a 2.5D or 3D package and change the stress levels again. The yields change at every level,” he said.

Campbell believes that the whole system has to be interactive. “Until 28nm, you didn’t need to have that interactivity. But as we go deeper and deeper into submicron technology, the interactivity between the package, the system and the silicon itself—and the basic R&D for the silicon – all have to start to play together or else at the end we’ll end up with gaps in the system which will then add cost to the deliverables that we have to bring to the marketplace,” he said.

ASE’s Calvin Cheung said the company’s biggest concern was CPI (chip package interaction). “We are really pushing assembly and test technology capabilities,” he said. “In the case of 2.5D, we have connect a couple hundred thousand interconnects and put them on a very, very small space. With the scaling, the die is getting smaller but your I/O density continues to increase.”

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