IEDM 2015 Slide 17: 3D Views of Nanoscale Devices

17. 3D Views of Nanoscale Devices
Category: Noteworthy Papers on Diverse Topics

Two noteworthy IEDM papers will describe different ways to generate highly accurate 3D views of extremely small devices, as an aid to ultimately boosting their performance.

3D Maps of TFET Heterojunctions
Paper 14.2 – Tunnel Junction Abruptness, Source Random Dopant Fluctuation and PBTI Induced Variability Analysis of GaAs0.4Sb0.6/In0.65Ga0.35As Heterojunction Tunnel FETs; R. Pandey et al, Pennsylvania State University

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Tunneling field-effect transistors (TFETs) are an emerging technology based on principles of quantum mechanics. TFETs are promising for ultra-low-power applications but improvements in their performance and reliability are needed. Critical to TFET performance when they are made from combinations of III-V materials is the need for abrupt and uniform interfaces among the dissimilar materials. Variability at these interfaces, or heterojunctions, reduces device performance. It is difficult to characterize heterojunctions with precision in nanometer-scale devices, but a Penn State team used atom probe tomography and time-of-flight spectroscopy to do so. First they cooled TFET samples to 50° Kelvin. Then, they rapidly heated the heterojunction under study with laser pulses to evaporate layers of atoms from it, one layer at a time. They captured the atoms from each layer in an electric field, and then performed spectroscopic analysis to identify the individual atoms which constituted each layer. From all this data they built a 3D map of the heterojunction, with a resolution of 2.4nm. They also studied two other sources of variability in TFETs—random dopant fluctuations and the interface between the channel and the ultra-thin high-k gate dielectric—with an eye toward further improvements.

3D Carrier Profiling in 10nm FinFETs
Paper 14.1 – Scalpel Soft Retrace Scanning Spreading Resistance Microscopy for 3D-carrier profiling in sub-10nm WFIN FinFET; Pierre Eyben et al, Imec

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In solid state devices, electrons and holes are generically called charge carriers. As 3D devices such as FinFETs scale to the 7nm and 5nm nodes, fewer charge carriers are available. Because their distribution is not uniform, it becomes critical to establish correlations between their actual locations within the 3D architecture and the device’s electrical performance. Once these correlations are known, the architecture can be modified for better performance. Scanning Spreading Resistance Microscopy (SSRM) is a technique that uses a probe to measure a surface’s electrical resistance and thus the density of charge carriers at any given point on the surface. An Imec team will discuss a variation of the technique they call Scalpel SSRM, which uses diamond-based probe tips to scrape off material as the surface is repeatedly scanned on all sides, thus probing deeper into the material layer by layer. They used the resulting data to produce accurate 3D maps of the density of charge carriers throughout sub-10nm FinFETs. They say their existing technique can be used to profile carrier density in 3D devices as small as 4nm, and that it has the potential to achieve a resolution of just 1nm, which would make it useful for characterizing extremely small future architectures such as gate-all-around arrangements and nanowires.


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