Variation in build-up substrate layer thicknesses and its impact on FCBGA BLR performance

Subtleties in thicknesses between the alternating Cu metal and dielectric layers within a build-up substrate can impact BLR performance.

BY JAIMAL WILLIAMSON, Texas Instruments, Dallas, TX

Managing an organization in an orderly and disciplined manner is known as “running a tight ship.” This mentality and discipline cannot be understated with build-up substrate supplier capability and manufacturing tolerances as it relates reliability and margin in a flip chip ball grid array (FCBGA) device. Build-up substrate technology is the backbone for flip chip packaging due to its ability to bridge high density interconnects and functionality enabling improved electrical performance in tandem with the semiconductor chip. Alternating metal and dielectric layers build up the substrate into the final composite structure. The range of thicknesses of the aforementioned metal and dielectric layers are dependent on associated substrate manufacturer design rules, which can have an impact on board level reliability (BLR). Having a keen awareness of substrate supplier design rules can aid not only troubleshooting, but improve understanding of reliability margin from a chip to package interaction standpoint for any array of commercial and automotive FCBGA applications.

Influence of copper and dielectric layers on reliability

To better understand the thickness variation impact of bottommost substrate copper (Cu) metal (15 +/- 5μm) and dielectric (30 +/-6μm) layers as it relates to strain energy density of BGA solder joint at die shadow area and package corner, a 3×3 factorial design of experiments (DoE) approach (FIGURE 1) was pursued. Through the use of finite elemental modeling, outputs of the study included both strain energy density under -40°C to 125°C and 0°C to 100°C BLR temperature cycle conditions and changes in coefficient of thermal expansion (CTE) as Cu metal and dielectric thicknesses varied. For the remainder of the article, results from the more stringent -40°C to 125°C BLR temperature cycle condition will be discussed.

FIGURE 1. 3x3 factorial DoE.

FIGURE 1. 3×3 factorial DoE.

Rationale of the study was based on a striking difference in BLR performance from two FCBGA daisy chain test vehicles having an identical substrate design, but manufactured at two different substrate suppliers (noted as supplier A and B in this article). The FCBGA daisy chain test vehicle comprises the following package attributes (see FIGURE 2 for a side view example):
• 40mm x 40mm body size
• 8-layer build-up stack (3/2/3)
• 400μm core thickness
• 1mm BGA pitch

FIGURE 2. Example of FCBGA package.

FIGURE 2. Example of FCBGA package.

Weibull analysis was generated from empirical BLR results at 5 percent and 63.2 percent cycles to failure. Specifically, at 5 percent cycles to failure supplier A exhibits ~25 percent reduced BGA solder joint fatigue life than counterparts from supplier B (as illustrated in FIGURES 3 and 4).

FIGURE 3. Weibull plot of supplier A.

FIGURE 3. Weibull plot of supplier A.

FIGURE 4. Weibull plot of supplier B.

FIGURE 4. Weibull plot of supplier B.

In a similar study focusing on component level reliability (CLR), it was observed that bottommost substrate Cu layer thickness can impact stress underneath die shadow area. For these reasons, a more detailed examination was done to measure bottommost substrate Cu layer thickness from daisy chain units of suppliers A and B. Based on package construction analysis, supplier A was found to target the nominal value of 15μm; whereas supplier B targeted the high end of specification at 20μm. These Cu thickness differences would play a significant role in the BLR results.

Stress modeling results

Outputs of the finite elemental modeling are revealed in FIGURE 5 based on inputs from the aforementioned 3×3 factorial DoE illustrated in Fig. 1. Based on the combi- nation of various Cu and dielectric layer thicknesses evaluated, thicker dielectric and Cu layers yield higher macroscopic CTE values. This is an expected trend based on CTE material properties of Cu and dielectric layers in relation to the substrate core material. Simulation results confirmed CTE in ascending order is: dielectric layer > Cu layer > substrate core. Comparing Weibull analysis from supplier A and B (figures 3 and 4), DoE legs 4 and 6 match best, respectively, to the empirical BLR results. In addition, DoE legs 4 and 6 align with the bottommost substrate Cu layer thickness values from the aforemen- tioned package construction analysis measurements. It is noted that based on modeling results, an approximately 2 percent change in CTE can swing the cycles to failure at 63.2 percent by ~11 percent. DoE leg 4 focuses on nominal Cu thickness of 15μm; whereas leg 6 focuses on the high end of the Cu thickness tolerance at 20μm. Dielectric thickness is nominal value of 30μm in both DoE cases. Improved BLR performance from supplier B is attributed to the thicker Cu providing a better CTE match to the BLR test board.

FIGURE 5. Finite elemental modeling results.

FIGURE 5. Finite elemental modeling results.

Use of JMP for statistical perspective

As a supplemental tool for data interpretation, JMP statistical analysis was performed to illustrate how nominal and extreme values of the metal and dielectric layer thickness specification affect FCBGA BLR performance. Analyzing the strain energy data outputs, the model fit well to the predicted values as shown in FIGURE 6. Similarly, CTE correlated well with predicted values as illustrated in FIGURE 7. Use of the prediction profiler function, as illustrated in FIGURE 8, shows CTE is proportional to increase in metal and dielectric thickness, which correlates with the stress modeling results.

FIGURE 6. JMP model of SED predicted vs. actual.

FIGURE 6. JMP model of SED predicted vs. actual.

FIGURE 7. JMP model of CTE predicted vs. actual.

FIGURE 7. JMP model of CTE predicted vs. actual.

FIGURE 8. CTE prediction as a function of metal and dielectric thickness

FIGURE 8. CTE prediction as a function of metal and dielectric thickness

Summary

Subtleties in thicknesses between the alternating Cu metal and dielectric layers within a build-up substrate can impact BLR performance. Two identical daisy chain substrate designs manufactured by different suppliers were compared head to head. A detailed package construction analysis revealed differences in bottommost Cu thickness layer within the substrate. This Cu thickness delta between the two substrate designs caused a change in CTE with supplier B (higher value) than supplier A due to thicker copper. Finite element modeling demon- strated relatively small macroscopic changes in CTE on the order of less than 2 percent can affect cycles to failure by 11 percent.

The key takeaway found from the head to head evaluation was supplier A producing a more stable process as it was able to meet the center point of the Cu thickness specification as compared to supplier B, which was off target. However, in essence, supplier A lost the head to head BLR comparative study with supplier B as its accuracy in meeting the Cu thickness target caused reduced solder joint fatigue life. The typical corrective action would be to work with supplier B to establish better tolerance control in their Cu plating process to stabilize Cu thickness at the center or nominal value like supplier A. However, the lesson learned was to tailor and control the Cu thickness at the higher end of the specification to improve reliability performance. Typically, in any setting the criteria of success is to hit the bullseye or target, which supplier A achieved. Conversely, supplier B missed this mark with results that were skewed to the right. Ironically, because of the skewed results off-target reliability margin was obtained. In reflection of these findings, the adage “success is in the eyes of the beholder” has never been more poignant.

JAIMAL WILLIAMSON is a packaging engineer responsible for development and qualification of Embedding Processing FCBGA devices within Texas Instruments’ Worldwide Semiconductor Packaging group.

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One thought on “Variation in build-up substrate layer thicknesses and its impact on FCBGA BLR performance

  1. Jevella Williamson

    Kudos to Mal!!! This article is excellent and exceptional as it represents and embodies all of your years of research from IBM/East Fishkill, New York to Texas Instruments in Dallas, Texas. What a marvelous job! I am sooooo proud of you! What can I say _ this is my son!

    Reply

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