The Symposium on VLSI Technology: Technical highlights

Papers that address the theme “Inflections for a Smart Society” are highlighted.

The 2016 Symposium on VLSI Technology is part of a premiere international conference that defines the pace, progress and evolution of micro-electronics, scheduled from June 13-16, 2016 in Honolulu, Hawaii and held in conjunction with the Symposium on VLSI Circuits (June 14-17, 2016). The Symposia’s overall theme “Inflections for a Smart Society,” reflects the industry’s transition point as “smart” system level applications help to transform the industry.

Samsung Electronics will present a 10nm logic technology developed using 3rd generation Si FinFETs for low power, high performance applications, demonstrating a speed improvement of 27% with a 40% reduction in power compared to 14nm process, achieved with multi-threshold voltage devices and reduced contact resistance (FIGURE 1). Overcoming process challenges such as multiple patterning, high aspect ratio etching, niche gate replace- ments, and advanced isolation, the authors demonstrated yield analysis of a 0.04μm2 SRAM with 128Mb cell size and observed a static noise margin of 190mV at 0.75V.

Screen Shot 2017-04-21 at 11.23.22 AM

TSMC will demonstrate a fully functional 32Mb 6-T high density SRAM with smallest reported size of sub-0.03μm2 using bulk CMOS FinFETs scaled beyond the 10nm node (FIGURE 2). This presentation also reports improved transistor performance and electrostatic control through process and CET optimization of scaled FinFETs with competitive performance: DIBL of <45mV/V, sub-threshold swing of <65mV/decade, and static noise margin of ~90mV for the high density SRAM operated at 0.45V.

Screen Shot 2017-04-21 at 11.23.27 AM

IBM and GLOBALFOUNDRIES developed the fundamental and disruptive enhancement of transistor mobility needed to continue expected power and performance scaling at 10nm and beyond, with the introduction of high mobility SiGe channel (20%Ge) into the PFETs to achieve 35% hole mobility increase, and thus ~17% PFET Ieff enhancement. The presentation will demonstrate for the first time10nm FinFET CMOS technology featuring SiGe channel PFETs with superior NBTi reliability and defect control.

TSMC will present a systematic study of the material properties, dimension effects and device characteristics of its In0.53Ga0.47As FinFETs, manufactured on 300mm Si substrates that demonstrate high performance with good uniformity across the wafer. High electron mobility III-V semiconductors are one potential path for continuing Moore’s Law to meet the high performance and low power requirements of future logic applications. Creating high quality hetero-epitaxial of III-V material on large scale Si platforms with good HK/III-V interfaces are critical hurdles to overcome for fabricating HP devices capable of replacing Si FF as scaling continues beyond 7nm.

Significantly, the devices fabricated on 300mm Si show similar characteristics in SS and Ion when benchmarked with equivalent devices fabricated on lattice-matched InP substrates. The current drive of the III-V FinFETs is Ion=44.1uA per fin for a fin-height of 70nm and a fin-width of 25nm. These results are among the highest values reported for In0.53Ga0.47As FinFETs.

Researchers at IBM will demonstrate for the first time high Ge content (HGC) SiGe FinFETs in a replacement mode high-k and metal gate (RMG) process flow with an aggressive equivalent oxide thickness (EOT) scaling down to 0.7nm. IBM’s first of its kind HGC SiGe pMOS FinFETs exhibits high mobility, record-low RMG long channel SS=66mV/dec and good short channel behavior down to Lg=21nm.

The devices are characterized down to 4nm fin widths with excellent mobility (μeff=220cm2/V-s) and reliability at 0.7nm. A 10-year lifetime target is achieved for sub-10nm FinFET widths.
This work demonstrates best mobility values compared to state-of-the-art FinFETs, ultra thin body Si or Ge alternatives, as well as to strained SiGe quantum well options, showing that high performance SiGe FinFETs are feasibile at these aggressive dimensions, with results that outperform all previously reported data.

A team from imec reports on vertically stacked gate- all-around (GAA) n- and p-MOSFETs of 8nm diameter with nanowire stacking and replacement metal gate (RMG) processing, which is relevant for continuing scaling beyond sub-10nm technology (FIGURE 3). Stacking nanowire GAA devices is a promising path to maximize current drive per footprint. Fabricated by adapting a RMG FinFET process, these devices represent an evolutionary approach to extend the learning achieved with FinFET manufacturing. The nanowires exhibit excellent short channel characteristics (SS=65mV/dec, DIBL=42mV/V for Lg=24nm) at performance levels comparable to FinFET devices. The parasitic channel below the nanowires is suppressed by a groundplane doping technique prior to nanowire specific processing.

Screen Shot 2017-04-21 at 11.23.35 AM

Intel’s corporate research group shows performance, area, and energy efficiency are improved by novel tunnel FET (TFET) library circuits, redesign of logic at low-VDD and CMOS/TFET heterogeneous logic. The TFET/CMOS logic with low-overhead level-shifters improves performance 50% while reducing energy 42% for non-critical perfor- mance logic. Performance and power are benchmarked by design synthesis using industry test cases, libraries and interconnect.

TDK Headway Technologies returns to the VLSI Symposium to present advances in writing speed of their perpendicular spin-transfer torque magnetic memory (pSTT-MRAM), which can be reduced to a pulse width of 750ps without compromising functionality and data retention. The switching of the full 8MB array with 80nm devices can be achieved with 3ns pulses without use of error-correcting code (ECC), with the array level data retention showing a 10-year lifetime at 1ppm at 125oC.

They demonstrate sub-ns switching of pSTT-MRAM over a large temperature range after optimization of the magnetic tunnel junction (MTJ) stack, with single devices switched reliably using write pulse length down to 750ps while preserving functionality and data retention @125oC.
This pSTT-MRAM with improved writing speed is a viable candidate for replacement of LCC cache for advanced technology nodes, as well as a possible replacement for non-volatile memory.
A novel perpendicular magnetic tunnel junction (MTJ) is demonstrated by Toshiba with a high speed cache memory operation around 1ns, low power switching less than sub-100μA and size scalability of write current down to 16nm diameter MTJ. This novel MTJ is suited for embedded NVRAM solutions for sub-20nm high-perfor- mance CMOS SoC technology.

Macronix and IBM investigate methods of reducing programming power in phase change memories (PCM) for new storage class memory (SCM) applications. The researchers demonstrate a new low power phase change memory using inter-granular switching (IGS), a novel 3D network of crystallites with phase change confined to grain intersections. Contrary to conventional phase change memories, for which an entire volume of chalco- genide glass is amorphized or crystallized to achieve high or low resistance, they propose a multi-grained structure where the phase change occurs only in the inter-grain regions. By localizing the phase- change to the inter-grain area, the reset power is substantially reduced to 20μA, as well as the thermal disturbance to the neighboring bits, with set speed and cycling endurance also enhanced.

CEA Leti and STMicroelectronics demonstrate for the first time a full 3D VLSI CMOS-over- CMOS integration, CoolCubeTM, on 300mm wafers, with the top level CMOS devices fabricated using low temperature (less than 650°C) processes. A functional 3D inverter with either PMOS over NMOS or NMOS over PMOS is demonstrated to achieve compatible performance with state-of-the- art high performance FDSOI devices. Furthermore, the Leti/STM work demonstrates the integration feasibility of CoolCubeTM by transferring a high quality Si layer over the 28nm devices with W-M1 and then returning to the front end of the line for processing the top CMOS devices.

For the first time, researchers at Stanford and National Nano Device Laboratories have developed a four-layer HfOx-based 3D vertical RRAM, the “tallest” one ever reported, integrated with FinFET selector (FIGURE 4). The four-layer 3D RRAM is a versatile computing unit for (a) brain- inspired computing and (b) in-memory computing. Uniform memory performance across four layers is obtained (±0.8V switching, 106 endurance, 104s @125°C). The 3D architecture with dense and balanced neuron-synapse connections provides 55% energy delay product (EDP) savings and 74% VDD reduction (enhanced robustness) as compared with conventional 2D architecture.

Screen Shot 2017-04-21 at 11.23.39 AM


Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.

Leave a Reply

Your email address will not be published. Required fields are marked *


Introducing Semiconductor Digest
04/30/2019Semiconductor Digest is a new magazine dedicated to the worldwide semiconductor industry...
KLA-Tencor announces new defect inspection systems
07/12/2018KLA-Tencor Corporation announced two new defect inspection products at SEMICON West this week, addressing two key challenges in tool and process monit...
3D-Micromac unveils laser-based high-volume sample preparation solution for semiconductor failure analysis
07/09/2018microPREP 2.0 provides order of magnitude time and cost savings compared to traditional sample...