Packaging and displays drive new litho requirements

By Pete Singer, Editor-in-Chief

Fan-out wafer level packaging (FOWLP) is gaining traction, leading to higher I/Os and larger formats, and new mobile displays are pushing the limits of pixel per inch (PPI) while also moving to larger formats. Both trends are driving new requirements for lithography equipment, including steppers, track systems and photoresists. Both packages and displays are employing new types of materials and thinner substrates as well. “There’s a lot of commonality between the advanced display technologies and packaging technologies,” said Rich Rogoff, vice president and general manager of Rudolph’s Lithography Systems Group. “The step-and-repeat system approach is ideally suited to address those challenges.”

Key lithographic challenges of advanced packaging and displays are shown in Figure 1.

Figure 1. Key lithographic challenges of advanced packaging and displays are shown.

Figure 1. Key lithographic challenges of advanced packaging and displays are shown.

Rogoff said another big challenge is the ability to manage what he calls dimensionally unstable material. “These are materials that change with time, with temperature, with humidity and with process steps, every time they come back through a lithography step they can change form. Steppers have to be able to deal with that,” he said.

Rogoff also said he’s seeing changes in imaging chemistries which are creating another challenges. “We’re doing things now from broadband resist to i-line resist, from thin-films to thick films, to dry films to organic chemistries. It’s all over the field here with respect to what types of chemistries are being used to image, and the challenge is of course when going from a thick material to a thin material and varied compositions, you get a much different kind of imaging characteristic. Really you need to be able to manage all of those without having to change your lithography system,” he said.

In packaging applications, large topography is yet another challenge. In a fan-out type of situation, there can be significant differences in heights between the substrate and the die, for example. “You’re having to image through, in some cases, >20 microns of photoresist for a two or three micron line, and that becomes a very big challenge,” Rogoff said. “The package size and the display sizes are also getting bigger, and so you need to try to get as much as you can into one imaging field. The lenses need to have a very large field of view.”

FOWLP, where individual die are connected on redistribution layer, is expected to lead to a major change in process equipment. Today, die are “reconstituted” on a wafer. In the future, as volume increases, a move to high density panels is expected. “As the demand goes up, certainly panels make the most sense,” Rogoff said.

Earlier this year, Rudolph announced that a leading outsourced assembly and test facility (OSAT) has placed an order for the JetStep Lithography System for the semiconductor advanced packaging industry’s first panel manufacturing line. “That’s the first true panel fan-out application that’s moving forward, especially in the OSAT world,” Rogoff said.

While the stepper part of the litho equation is ready for “panelization,” the rest of the industry infrastructure is working from two directions. One, from printed-circuit board type solutions where thick resist are dry films. The other, from the display side, uses thin chemical resists. “Somehow we have to bridge the gap between a thin film and a thick film,” Rogoff said. “These are some of the infrastructure things that are still being worked out, but I think those are relatively easy to solve.”

Elvino da Silveira, Rudolph’s vice president of marketing, said he’s seen some recent changes. “Last year, when we were talking to the various customer and partners that we interact with in terms of the panel level fan out, everybody was really focused on doing reconstituted panels, the face-down type chips. Basically taking the EWLB process and scaling it up to the panel level. As time has gone on, and with TSMC bringing out InFO and so forth, there have been several players that are more open to doing this on a carrier. It adds some costs, but at least based on the general feedback we’ve gotten from some of the industry , scaling up to the larger substrate offsets the additional cost of the carrier,” he said.

Figure 2 (presented at SEMI’s Industry Strategy Symposium in January by Babak Sabi, corporate vice president, director, assembly and test technology department, Intel Corp.) shows the expected progression of packaging technology as IO density increases. Flip chip, ball grid array on the left (the orange box) has 15-60 micron feature sizes depending on the layer and the type of feature being exposed.

Figure 2. As IO density increases, new packaging technologies will be required (SWIFT, SLIT, SLIM and INFO-WLP are trademarks of Amkor, ASE and TSMC). Source: Intel (SEMI Industry Strategy Symposium 2016)

Figure 2. As IO density increases, new packaging technologies will be required (SWIFT, SLIT, SLIM and INFO-WLP are trademarks of Amkor, ASE and TSMC). Source: Intel (SEMI Industry Strategy Symposium 2016)

The next generation, (the yellow box) indicates fan out packaging. “We’re still more towards that boundary between the orange and the yellow, because really no one’s producing sub-five microns in HVM today. Most of it is between 5 and 10,” da Silveira said.

The next level (the green box) indicates embedded technology, such as Intel’s Embedded Multi-die Interconnect Bridge (EMIB). Instead of using a large silicon interposer typically found in other 2.5D approaches, EMIB uses a very small bridge die, with multiple routing layers. Here, the IOs are getting much higher, and the feature sizes are getting pushed toward two microns. As technology moves from the yellow box to the green box, expect a switch from wafers to panels.


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