Technology and Design Architectures and Process Innovations for 7 and 5nm BEOL Interconnects

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Date: September 14, 2016 at 1 p.m. ET

Free to attend

Length: Approximately one hour

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For a semiconductor technology node, the BEOL definition must support minimal parasitic impact to technology, sufficient reliability, required dimensional scaling from previous nodes for standard cell and custom logic requirements, and high yielding/low cost integration schemes. This webcast will discuss the key BEOL elements and innovations in these areas for the 7nm nodes and beyond. The individual elements are often in conflict with each other, but must be considered in unison to determine the overall best definition.

Speaker:

Larry ClevengerLarry Clevenger, Ph.D., Senior Technical Staff Member , 5nm, 7nm, 10nm and 14nm BEOL Architect, IBM Research

Dr. Larry Clevenger is an internationally recognized leader in semiconductor technology – taking new products from innovation to definition to early production. Since 2000 he has defined new semiconductor technologies for IBM as a chip hardware lead architect. His area of excellence is optimizing the on-chip interconnect from silicon devices to semiconductor packaging substrates for performance, yield, and cost. He is a member of the IBM Academy of Technology and he is a life time IBM Master Inventor, with over 230 issued patents. Dr. Clevenger received a B.S. in Material Engineering from UCLA and a Ph.D. in Electronic Materials from MIT.

Sponsored by Air Products

Air Products has been a leading global supplier of high-purity gases, chemicals, and delivery systems to the electronics industry for over 40 years. We serve all major segments of the industry with a unique combination of offerings, experience, and commitment.  We’re advancing materials science. We’re advancing semiconductors. We’re advancing mobility. What can we help you advance?  www.airproducts.com/advancing

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One thought on “Technology and Design Architectures and Process Innovations for 7 and 5nm BEOL Interconnects

  1. Byung Chun Yang

    Thank you for the chance for discussion. I have a question to Dr. Clevenger. Isn’t there a chance for Cu contamination to PLK dielectric materials when you open a barrier layer at the bottom of via opening in a RIE process for forming a damascene opening? I believe even if the RIE system detected a Cu signal using EPD system, the barrier open process would be pursued longer, so that every via hole is completely opened. This is needed to increase via yield, but the Cu contamination is inevitable as we run more barrier opening process beyond the time when the first via hole was exposed. Once again, is this kind of Cu contamination exerting any bad Cu contamination to PLK so that device property would be adversely impacted? Thanks for answering in advance. Byung Chun Yang

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