Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced several new capabilities resulting from its close collaboration with TSMC to further 7nm FinFET design innovation for mobile and high-performance computing (HPC) platforms. The Cadence digital, signoff and custom/analog tools have achieved certification for v1.0 Design Rule Manual (DRM) and SPICE certification for the TSMC 7nm process. Cadence has also delivered solutions for a new process design kit (PDK) enabling optimal power, performance and area (PPA) when designing with TSMC’s 7nm process. In addition, the Cadence 7nm Custom Design Reference Flow (CDRF) and the library characterization flow have been enhanced, and its 7nm DDR4 PHY IP is in deployment with customers.
7nm Tool Certification Cadence provides a fully integrated digital flow from implementation to final signoff that has been certified by TSMC for the 7nm process. The digital flow includes the Innovus Implementation System, Quantus QRC Extraction Solution, Tempus Timing Signoff Solution, Voltus IC Power Integrity Solution, Voltus-Fi Custom Power Integrity Solution, Physical Verification System (PVS) and Layout-Dependent Effect (LDE) Electrical Analyzer.
Support for TSMC’s 7nm HPC platform includes via-pillar modeling in the Genus Synthesis Solution and full via-pillar-capable implementation and signoff environments. Additionally, clock-mesh handling and bus-routing capabilities in the tools support the high-performance library to deliver better PPA and mitigated electromigration (EM). These capabilities enable customers to successfully design advanced-node systems while reducing iterations and achieving cost and performance objectives.
The certified custom/analog tools include the Spectre Accelerated Parallel Simulator (APS), Spectre eXtensive Partitioning Simulator (XPS), Spectre Classic Simulator, Virtuoso Layout Suite, Virtuoso Schematic Editor, and Virtuoso Analog Design Environment (ADE). Enhancements made for the 7nm process include advanced device snapping and an accelerated custom placement and routing flow that enables customers to improve productivity and meet power, multiple patterning, density and EM requirements.
7nm CDRF Delivery Cadence delivered an enhanced Custom Design Reference Flow (CDRF) to address 7nm custom and mixed-signal design challenges. The CDRF incorporates advanced methodologies and features that provide productivity improvements through a series of in-depth “how-to” circuit design, layout implementation, and signoff and verification modules. The circuit design module covers “how-to” topics, such as capturing schematics with device arrays using module generator (ModGen) constraints and the TSMC PDK, functional verification, yield estimation and optimization, and the latest reliability analyses. For signoff verification, the physical verification modules highlight design rule and layout-versus-schematic (LVS) checking, signoff parasitic extraction, and electromigration and IR drop (EM/IR) signoff checks.
The layout implementation module includes connectivity and constraint-driven layout for FinFET device placement, enabling designers to avoid design rule violations and address layout-dependent effects (LDEs). The routing module offers a color-aware flow and an innovative track-pattern system that reduces design time, mitigates parasitics and helps designers avoid EM issues.
7nm Library Characterization Tool Flow Delivery In addition to tool certification, the Cadence Virtuoso Liberate Characterization Solution and the Virtuoso Variety Statistical Characterization Solution have been validated to deliver Liberty libraries for the TSMC 7nm process including advanced timing, noise and power models. The solutions utilized innovative methods to characterize the Liberty Variation Format (LVF), enabling process variation signoff and the ability to create EM models enabling signal EM optimizations and signoff.
7nm IP Collaboration As a leader in DDR controller and PHY IP, Cadence has deployed its DDR4 PHY and LPDDR4 PHY in multiple generations of TSMC process technologies, ranging from 28HPM/28HPC/28HPC+ to 16FF+/16FFC nodes. Through close collaborations with TSMC and customers, Cadence began developing IP on the 7nm process last year. Cadence has taped out its flagship DDR4 PHY using the 7nm process node in Q4 2016, and key customers have integrated the 7nm DDR PHYs into their enterprise-class SoCs.
“TSMC’s latest process advancements combined with enhancements to Cadence tools and IP offer our mutual customers optimal solutions for advanced-node designs,” said Dr. Anirudh Devgan, executive vice president and general manager of the Digital & Signoff Group and the System & Verification Group at Cadence. “This certification and the v1.0 process maturity milestone represent our readiness to meet the production needs of our most innovative customers using the 7nm process.”
“The availability of new v1.0 design rules and PDK indicates that we’ve reached a new pinnacle with 7nm production designs,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “We’ve collaborated closely with Cadence to certify its tools and deliver IP innovations for 7nm designs, which enable our customers to achieve their PPA objectives with mobile and HPC designs.”
“ARM has collaborated closely with Cadence and TSMC to enable a 7nm design flow for our joint customers,” said Monika Biddulph, general manager of the Systems and Software Group, ARM. “This flow is enabling the development of platforms for high-end mobile and high-performance computing applications.”