FET fabrication from fins to nano-sheets

By Ed Korczynski

As the commercial IC fabrication industry continues to shrink field-effect transistor (FET) sizes, 2D planar structures evolved into 3D fins which are now evolving into 3D stacks of 2D nano-sheets. While some researchers continue to work on integrating non-silicon “alternate channel” materials into finFETs for next generation logic ICs, published results from labs around the world now show that nano-wires or nano-sheets of silicon will likely follow silicon finFETs in high-volume manufacturing (HVM) fabs. 

Today’s finFETs are formed using self-aligned multi-patterning (SAMP) process flows with argon-fluoride immersion (ArFi) deep ultra-violet (DUV) steppers to provide arrays of equal-width lines. A block-mask can then pattern sets of lines into different numbers of fins per transistor to allow for different maximum current flows across the chip. When considering the next CMOS device structure to replace finFETs in commercial HVM we must anticipate the need to retain different current flows (ION) across the IC.

Gate-all-around (GAA) FETs can provide outstanding ION/IOFFratios, and future logic ICs could be built using either horizontal or vertical GAA devices. While vertical-GAA transistors have been explored for memory chips, their manufacturing process flows are significantly different from  those used to form finFETs. In contrast, horizontal-GAA FETs processing can be seen as a logical extension of flows already developed and refined for fin structuring.

“With a number of scaling boosters, the industry will be able to extend finFET technology to the 7 or even 5nm node,” said An Steegen, EVP at imec’s Semiconductor Technology and Systems division. “Beyond, the gate-all-around (GAA) architecture appears as a practical solution since it reuses most of the finFET process steps.”

The figure shows simplified cross-sections of a finFET with fin height (FH) of 50 nm along with two different stacks of lateral nano-sheets (LNS, also known as horizontal nano-sheets or HNS), where the current flows would be normal to the cross-section. HNS are variations of horizontal nano-wires (HNW) with the wires widened, shown as 11nm and 21nm in the figure. The HNS are epitaxial-silicon grown separated by sacrificial sacrificial silicon-germanium (SiGe) spacer layers.

Cross-sectional schematics of idealized (left) 50nm high finFET, (center) 5nm high by 11nm wide lateral-nano-sheets at 12-18nm vertical pitch, and (right) lateral-nano-sheets 21nm wide. (Source: imec)

In an exclusive interview with Solid State Technology, Steegen discussed a few details of the process extensions needed to convert finFETs into HNS-FETs. The same work-function ALD metals can be used to tune threshold voltages such that one epi-stack process can grow silicon for both n-type and p-type FETs. Happily, no new epitaxial reactors nor precursor materials are needed. Isotropic etch of the SiGe vertical spacers, and then filling the spaces with a dielectric deposition may be the only new unit-processes needed.

Alternate channel wires and sheets

At the 2018 Symposia on VLSI Technology and Circuits, imec presented two papers on germanium as an alternate channel material for nanowire pFET devices. In the first paper they studied the electrical properties of strained germanium nanowire pFETs as high-end analog and high-performance digital solutions. The second paper demonstrated vertically-stacked GAA highly-strained germanium nanowire pFETs.

The commercial IC fab industry has considered use of alternate channels for planar devices and for finFETs, yet so far has found extensions of silicon to work well-enough for pFETs. Likewise, the first generation of HNS will likely use silicon channels for both nFETs and pFETs. Germanium GAA pFETs thus represent the ability to shrink HNS devices for future nodes.

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