Material innovations for advancements in fan-out packaging

The development of a new class of materials with superior functionalities is essential to enable emerging process schemes for wafer- or panel-level FO packaging.

BY KIM YESS, Director of Technology Development, Wafer-Level Packaging Business Unit Brewer Science, Rolla, MO

Fan-out (FO) packaging is one of the most talked- about advanced packaging solutions for heterogeneous integration. Although it has been available for nearly a decade for the chips used in mobile devices, its popularity has spiked in the past two years, thanks to Apple’s adoption of TSMC’s integrated fan-out package-on-package (InFO PoP) for its A10 and A11 processors, and the Apple Watch. As a result, FO has quickly progressed to the mainstream, with outsourced semiconductor and test service providers (OSATs), foundries and integrated device manufacturers (IDMs) vying for market share.

What’s driving FO innovation?

According to Yole Développement, smartphone appli- cation processors are the main beneficiaries of high- density fan-out (HDFO)’s excellent performance and thin profile. As a result, as shown in FIGURE 1, the HDFO market was worth $500 million in 2017 and was predicted to exceed $1 billion if other players, namely Qualcomm, Samsung and Huawei switch to HDFO [1].

Jan Vardaman, TechSearch International, said Apple selected InFO PoP for its A10 processor because of power noise reduction and signal integrity improvement, in addition to being thin enough to enable a low-profile PoP solution as small as 15 x 15 mm.

In addition to HDFO, the market is growing for conventional FO, driven by new applications such as audio CODECs, power management ICs, radar modules and RF[2].

The automotive electronics market—particularly advanced driver assistance systems (ADAS) and autonomous vehicles—is also being explored as a viable application for FO because of the flexibility and fast time to market it provides, as well as the ability to adapt to new sensor system protocols.

Exploring new processes

In this race to provide the most reliable, highest-density solution, many manufacturing approaches have emerged. FO is not only becoming more versatile, it is also reaching high enough densities to offer a cost-effective alternative to 2.5D interposers. As the demand for FO increases, packaging processes are being explored in both the wafer and panel formats. This is driving a need for new and better-performing materials that address more stringent specifications to meet, for example, finer line and space requirements, as well as the improved elongation needed for advanced high-density FO.

Thanks to recent innovations in packaging materials, three new process approaches have been developed to bridge these gaps. One approach involves new carrier- assist release-layer materials for creation of the redistribution layer (RDL)-first/chip-last buildup processes. Another important development is an alternative to lithography dielectric patterning that uses laser-ablated dielectric materials. Lastly, an alternative to the molding process in the chip-first approach that uses a laminated die stencil and gap-fill materials is under development.

Carrier-assist release layer for chip-last FO

Low-density FO is built using a chip-first approach, which involves first placing the chips on a substrate wafer followed by over-mold to create a reconstituted wafer, with subsequent RDL and solder-ball placement. On the other hand, HDFO processes like TSMC’s InFO technology use a chip-last approach. Also known as RDL-first, this approach (with target features of ≤2 μm l/s) begins with a layer-by-layer buildup of the RDL on a carrier wafer, followed by die placement and over-mold.

Currently, manufacturers turn to permanent bonding, followed by backgrinding to remove the carrier wafer. This is because conventional temporary bond/debond materials cannot withstand the downstream RDL processes that subject the build-up layers to high temperatures and vacuum conditions, as well as harsh chemical environments. However, backgrinding is a destructive process, creating debris that can cause damage to the device itself.

The new approach uses neither a temporary nor a permanent bonding process. Instead, it utilizes a release layer on the carrier substrate to allow separation of the FO wafer from the carrier at the end of the process flow.

The challenge with this new method is designing a material that withstands high- temperature process steps as well as strong mechanical stresses without delaminating or distorting the reconstituted wafer. Additionally, the material must be adaptable to the new FO panel-level processes (FOPLP) along with existing round wafers, as the industry innovates in that direction.

Manufacturers are investigating the use of copper foil lamination, as an alternative to physical vapor deposition of the seed layer. The copper laminating process requires a material that is flexible enough to sufficiently laminate layers on top of the substrate, and that can be cured using UV radiation or heat to yield a structurally stable base that meets the thermomechanical and chemical resis- tance requirements of the build-up process.

Additionally, it must be releasable by ultraviolet(UV) laser ablation or other UV exposure. To meet these needs, a new class of so-called “triangle” polymeric materials has been conceived that have advantages over standard-application release layers because they are multi functional. Specifically, these “triangle” materials can be laminated, cured and debonded, adding flexibility to the carrier-assisted process (FIGURE 2).

Dielectric RDL patterning

Traditional RDL patterning uses a complicated, 24-step photolithography process that employs photosensitive dielectric materials and masks to create trace patterns, followed by Cu plating to route the signal from the chip out of the package to the solder balls. This process, developed with round wafers in mind, uses spin-coated dielectrics. Unfortunately, these lithography processes are too costly to utilize in innovative package designs that must meet the stringent requirements for most markets [3].

As the industry moves to HDFO and begins to investigate panel-level processes to reduce cost and improve yield, alternative patterning approaches are being developed that can achieve resolutions down to 5 μm with an ultimate goal of 2 μm l/s. Laser ablation is one alter- native to photolithography for creating finer-featured RDL patterns while achieving all these goals.

The combination of a high-power excimer laser source, large-field laser mask and precision projection optics enables the accurate replication and placement of fine resolution circuit patterns without the need for any wet processing. In addition, with excimer laser patterning technology, the industry gains a much wider choice of dielectric materials (photopatternable and non-photopatternable) to help achieve further reductions in manufacturing costs as well as enhancements in chip or package performance [4].

By using excimer laser ablation, many process steps and costly materials can be eliminated from the manufacturing flow, including resist coating, baking, developing and resist stripping and etching using harsh chemicals [5].

FIGURE 3 demonstrates the considerable cost savings of laser ablation over photolithography. Activity-based cost modeling was used to carry out the cost comparison between the two processes. With activity-based cost modeling, a process flow is divided into a series of activities, and the total cost of each activity is calculated. The cost of each activity is determined by analyzing the following attributes: time, amount of labor and cost of material required (consumable and permanent), tooling cost, all capital costs, and yield loss associated with the activity.

Laser-ablated patterning is a room-temperature process that works by using a dielectric material to build up RDL fixtures, and excimer and solid-state lasers to ablate the material and direct-write a pattern. Laser ablation allows for depth and side-wall angle control, making it possible to create feature sizes <5 μm. It also reduces chemical waste streams. Additionally, fewer steps, fast removal rates and high throughput lead to a lower-cost solution in comparison with traditional photolithography (Fig. 3).

Photosensitive dielectric materials often fall short of meeting the required mechanical and thermal properties, and therefore need a variety of process “work-arounds” that add to the cost of ownership. Alter- natively, non-photopatternable dielectric materials can be designed using a vast selection of chemical platforms, which improves the possibility of meeting the thermal and mechanical property requirements.

As with all new approaches, laser ablation is not without some challenges. Post-laser-ablation cleaning and debris removal, along with surface roughness as a result of the ablation step, need to be addressed. Additionally, the laser system needs to achieve a high ablation rate for high throughput. While the process costs of laser ablation are lower than photolithography, there is still a significant equipment capacity investment required to add laser tools to the manufacturing line. This may delay overcoming the most critical challenge: convincing the industry to embrace laser ablation patterning over conventional approaches.

Development of the dielectric material is ongoing to further push the resolution of laser-ablated materials. In addition to spin and spray coating, other deposition methods being investigated include slot-die coating, ink-jet printing, Vermeer coating, spray coating and laminate film.

Laminated polymeric die-stencil fill concept

Chip-first is the standard approach for conventional FO packages, including embedded wafer level ball grid arrays (eWLBs), redistributed chip packages (RCPs), M-Series and others. It calls for placing die into the mold compound before the RDL processing steps. One of the challenges of this approach that impacts final yield is the die shift that can occur during the RDL processes. Additionally, in multi-die FOWLP configurations that combine disparate technologies to essen- tially form a system-in-package (SiP), the dies may be of different sizes and heights. Additionally, the mismatch in coefficient of thermal expansion (CTE) between all of the materials involved leads to severe warpage of the reconstituted wafer.

A new carrier-based approach developed to combat this problem replaces the over-mold structure around the dies with a laminated die stencil (FIGURE 4). A release layer is first applied to a carrier, followed by a curable adhesive backing layer. Next, the die stencil film is laminated to the curable adhesive backing layer. The dies are then placed in the stencil openings and attached to the adhesive backing layer during thermal curing. The gaps between the dies and stencil are then filled with a flexible yet curable polymeric material, yielding a stable reconstituted substrate. This is followed by construction of the RDLs while still supported on the carrier. Finally, the reconsti- tuted substrate is released from the carrier.

The stencil can be fabricated as a sheet from a variety of high-temperature-stable thermoplastics including, for example, carbon-fiber-filled polyetheretherketone (PEEK), which has an in-plane CTE of <10 ppm/K.

The pre-formed cavities can be configured for different die sizes and types to fabricate SiP components. The curable adhesive backing layer is comparatively soft and tacky before it is cured. This property allows the die-stencil film to be laminated to the structure at low temperatures.

This process not only addresses the die shift issue that plagues the chip-first approach, it also enables varying levels of die thickness. When placed in the stencil, the polymeric material allows the dies to sink and adjusts itself within the stencil. Once the dies are set, the material is cured, which locks them in place. Additionally, the process offers high-temperature stability, better CTE matching for warpage control, and high throughput.

Summary and conclusion

Fan-out packaging is on track to be a game-changing advanced packaging technology that will enable heterogeneous integration architectures. Applications have already expanded beyond smartphones, with HDFO targeting emerging applications.

Substrate handling and RDL strategies will be increasingly important, if not critical, for both conventional and HDFO technologies. To this end, the development of a new class of materials with superior functionalities is essential to enable emerging process schemes for wafer- or panel-level FO packaging.

The gamut of application needs for wafer support includes simple thinning processes during the backside processing of ultrathin, 300-mm silicon wafers, as well as reconstituted substrates for RDL fabrication. In addition to new materials, novel manufacturing approaches are also needed to further optimize the FO process flow.

KIM YESS is Director of Technology Development, Wafer-Level Packaging Business Unit Brewer Science, Rolla, MO


The author would like to thank Amy Lujan, SavanSys, for her contribution to this article regarding activity- based cost modeling.


1. Yole Developpement, “Fan-out Packaging Confirms its Success Story,” 3D InCites, September 14, 2017.
2. P. Garrou, “ITLE 356 SEMI Taiwan Part 1: Fan-out Packaging Players, Applications, and Market Growth,” Solid State Technology, October 2017.
3. H.Hichri,M.Arendt,andM.Gingerella,“Novel Process of RDL Formation for Advanced Packaging by Excimer Laser Ablation,” 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, 2016, pp. 1733-1739. doi: 10.1109/ECTC.2016.225
4. H. Hichri, Ibid.
5. R. Zoberbier, M. Souter, “Laser Ablation, Emerging Patterning Technology for Advanced Packaging,” SUSS MicroTec Lithography GmbH, January 2010


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