By Dr. Phil Garrou, Contributing Editor
Samsung finally announces commercialization of TSV based DDR4
IFTLE has been reporting for awhile that a Samsung announcement of stacked memory based on TSV technology was imminent. [ see IFTLE 123 “Intels Bohr on 3DIC;Samsung DDR4 roadmap…” especially since similar announcements have already come from Micron and Hynix.]
On Aug 26, Samsung finally announced that it has started mass producing 64 GB DDR4, dual Inline memory modules (RDIMMs) that use 3D TSV technology. The new memory modules are designed for use with enterprise servers and cloud base solutions as well as with data center solutions [link]. The release is timed to match the transition from DDR3 to DDR4 throughout the server market.
Samsung has started operating a new manufacturing line dedicated to TSV packaging, for mass producing the new server modules. The new RDIMMs include 36 DDR4 DRAM chips, each of which consists of four 4-gigabit (Gb) DDR4 DRAM dies. The low-power chips are manufactured using Samsung’s most advanced 20-nanometer (nm) class* process technology and 3D TSV package technology.
The new 64GB TSV module reportedly performs twice as fast as a 64GB module that uses wire bonding packaging, while consuming approximately half the power.
Samsung believes that in the future it will create even higher density DRAM modules by stacking more than four DDR4 dies using 3D TSV technology.
Samsung has been working on improving its 3D TSV technology since it developed 40nm 8GB DRAM RDIMMs in 2010 [see IFTLE 65, “Samsung’s 32GB RDIMM DDR3…” ], and 30nm 32GB DRAM RDIMMs in 2011 using 3D TSV.
Amkor’s Liang says 3DIC will take another 3 yrs to get to HVM
At a press event held prior to the official opening of Semicon Taiwan 2014, Mike Liang, president of Amkor Technology Taiwan, announced that “demand of 3D ICs may take another 3 years due to concerns of high production costs.” He added that “…at present, only a few specific applications that require extremely high performance ICs require the use of 3D ICs, but the amount of such 3D ICs is not sufficient enough to support a full production line.” I’m sure this served to pour cold water on the subsequent 3DIC tech forum!
Intel Announces Embedded Multi die Interconnect (EMIB)
Intel recently announced that a new technology “Embedded Multi-die Interconnect Bridge” or EMIB will be available to 14nm foundry customers [link].
They claim it is a “… lower cost and simpler 2.5D packaging approach for very high density interconnects between heterogeneous dies on a single package.” While neither Intel nor any initial press reports gave any indication of exactly what this means.
It is highly likely that this is tied to the issuance of patent application publication US 2014/0070380 A1 published March 13 2014 [link].
In simplified form interconnect bridges (“silicon glass or ceramic”) are embedded in a laminate substrate and connected with flip chip as shown below:
A cross section of the package is more revealing showing connections through the laminate and connections through the bridge substrate (316) which would be TSV in the case of a silicon bridge substrate. The underside of the bridge substrate (314) may be connected to another bridge substrate for further interconnect routing as shown below.
While there is no silicon interposer, there do appear to be TSV in the embedded interconnect substrate as shown below. While removing complexity from the IC fabrication by eliminating TSV from the foundry process, the packaging operation becomes much more complex.
Since the 2.5D interposer has been reduced in size to the interconnect bridges, this may reduce cost, but will increase signal length vs a true 3D stack or a silicon interposer 2.5D
While Intel released the following description: “Instead of an expensive silicon interposer with TSV (through silicon via), a small silicon bridge chip is embedded in the package, enabling very high density die-to-die connections only where needed,” IFTLE thinks this is somewhat misleading.
The packaging analogy to what they have done is as follows:
A high density bumped chip could be put down on to a high density build up PWB, but in most cases the high density bumped chip is placed on a smaller BGA substrate which is then put onto a lower density, lower cost PWB. The latter is the lower cost solution. In this case, large expensive high density interposers are avoided, and the much smaller emib are used for the high density interconnect. It will be interesting to see what if any the cost differential will be here.
For all the latest in 3DIC and advanced packaging, stay linked to IFTLE…
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