Leti, a research institute at CEA Tech, has reported breakthroughs in six 3D-sequential-integration process steps that previously were considered showstoppers in terms of manufacturability, reliability, performance or cost.
CoolCubeTM, CEA-Letiâ€™s 3D monolithic or 3D sequential CMOS technology allows vertically stacking several layers of devices with a unique connecting-via density above tens of million/mm2. This MoreMoore technology decreases dice area by a factor of two, while providing a 26 percent gain in power. The wire-length reduction enabled by CoolCubeTM also improves yield and lowers costs. In addition to power savings, this true 3D integration opens diversification perspectives thanks to more integration of functions. From a performance optimization and manufacturing-enablement perspective, processing the top layer in a front end of line (FEOL) environment with a restricted thermal budget requires process modules optimization.
CEA-Letiâ€™s recent 3D sequential integration results were presented Dec. 3 at IEDM 2018 in the paper, â€śBreakthroughs in 3D Sequential Integrationâ€ť. The breakthroughs are:
- Low-resistance poly-Si gate for the top field-effect transistors (FETs)
- Full LT RSD (low temperature raised source and drain) epitaxy, including surface preparation
- Stable bonding above ultra low-k (ULK)
- Stability of intermediate back end of line (iBEOL) between tiers with standard ULK/Cu technology
- Efficient contamination containment for wafers with Cu/ULK iBEOL, enabling their re-introduction in front end of line (FEOL) for top FET processing, and
- Smart CutTM process above a CMOS wafer.
To obtain high-performance top FETs, low gate access resistance was achieved using UV nano-second laser recrystallization of in-situ doped amorphous silicon. Full 500Â°C selective silicon-epitaxy process was demonstrated with an advanced LT surface preparation and a combination of dry-and-wet etch preparation.Â Epitaxial growth was demonstrated with the cyclic use of a new silicon precursor and dichlorine Cl2 etching. At the same time, the project paved the way to manufacturability of 3D sequential integration including iBEOL with standard ULK and Cu-metal lines.
A bevel-edge contamination containment strategy comprised of three steps (bevel etch, decontamination, encapsulation) enabled reintroducing wafers in an FEOL environment following the BEOL process. In addition, the project also demonstrated for the first time the stability of line-to-line breakdown voltage for interconnections submitted to 500Â°C. The work also demonstrated a Smart CutTM transfer of a crystalline silicon layer on a processed bottom level of FD-SOI CMOS devices, as an alternative to the SOI bonding-and-etch back process scheme for top channel fabrication.