By Dick James, Senior Technology Analyst, Chipworks
It’s the time in the media world that we see a frenzy of predictions for the coming year. They are mostly business or tech trends, so I figured I might as well chip in (har! har!), and give a more detailed idea of what new semiconductor products we look forward to this year, now that we are in 2016.
This might seem to be a bit like fortune-telling, but it’s actually a compilation of the notes we’ve made from this year’s press announcements, coupled with the trends we’ve observed in our reverse engineering, and keeping an open ear at the industry events that we’ve attended.
Logic & Foundries
2016 will be a relatively quiet year when it comes to the leading-edge processes, since we do not expect to see a high-volume of 10 nm products this year. There has been a fair bit of comment that the upcoming Apple A10 processor might be on 10 nm this autumn, but to me it seems a real stretch to expect a full node advance barely 18 months after the introduction of a 14 nm product from Samsung, and a 16 nm product from TSMC, especially in the volume that Apple would require.
We do expect to see the second generation 14/16 nm processes, FinFET Plus (16FF+) from TSMC and 14LPP from Samsung and possibly their co-supplier GLOBALFOUNDRIES. The second-tier foundries such as UMC and SMIC will be ramping up their 28 nm high-k metal gate (HKMG) product, so we will be monitoring those as we get them. It appears that UMC will be skipping 20 nm and going straight to 14 nm, but that will not likely appear until 2017.
When it comes to fully depleted silicon on insulator (FD-SOI), we expect to see a mainstream 28 nm product this year, since Samsung has stated that they are producing, and have shipped more than a million wafers, with STMicroelectronics as one of their lead customers. Chipworks has already analyzed a custom 28 nm FD-SOI ASIC manufactured at STMicroelectronics, which was a simple implementation without back-bias. For the mainstream parts, we will be analyzing back-bias implementation, if found, as it is touted as one of the big advantages of FD-SOI.
GLOBALFOUNDRIES is also on the FD-SOI bandwagon, but they seem to be concentrating on their 22FDX™ processes. A number of the ASIC design houses are claiming to be designing into those, so with luck we will see some very early product by year-end.
There will also be a continued emphasis on low power variants of older generation processes, such as 40 and 55 nm, aimed at mobile/wearable devices where battery life is critical.
To finish up, another process sector where we expect to see development is radio frequency silicon on insulator (RF-SOI). We are already seeing the introduction of RF-SOI into products such as antenna switches for the RF front end of mobile phones.
This will be another year of evolution for dynamic random-access memory (DRAM), with the introduction of 1X nm generation memories by the big three (Micron, Samsung, and SK Hynix), although possibly not until year-end.
Micron has 1X and 1Y nm nodes in its roadmap (above), enabling 1X volume mid-2016.
Samsung predicts three 1X nm nodes (see above), though there is no time scale here; however, we already have their 20 nm part, which is in volume production, so it’s reasonable to expect a 1X nm part this year. We haven’t heard anything formal from SK Hynix, but again, we already have their 20 nm part, so we would expect a 1X nm device in 2016.
The other facet of the DRAM business is stacked memory using through-silicon vias (TSVs); in 2015 we saw the Samsung version, and the SK Hynix High Bandwidth Memory (HBM). We’re still waiting for the Intel/Micron Hybrid Memory Cube (HMC), and we expect to get our hands on that this year, as well as the HBM2 from SK Hynix AND Flash.
The big news in NAND flash memory is the introduction of 3D/vertical technology, with the bitcells stacked one above another instead of on the die surface. Samsung launched their V-NAND over a year ago, with 32 active layers in both multi-level cell (MLC) and tri-level cell (TLC) versions, using charge-trap storage technology. They are now shipping the third generation part (256 Gb) with 48 layers, so we should see that in the near future.
Last month, at IEDM (International Electron Devices Meeting), Intel/Micron detailed their 3D-NAND, a 32-layer device, this time using conventional floating gate charge storage. According to their investor calls, they are sampling these at the moment and should be shipping volume in the second half of this year.
SanDisk/Toshiba are also sampling, but their 3D-NAND is a 48-layer, 256-Gb TLC device, built using their own Bit-Cost Scalable (BiCS) charge-trap technology. They have been more cautious about the economics of launching 3D technology, but again I look forward to getting some in 2016. Last, but not necessarily least, SK Hynix claim that they are already in 3D production, and we should also see their floating-gate version this year.
In parallel, all the companies are still evolving planar flash products – we will likely find 13 – 15 nm planar flash chips being launched, since the 15/16-nm ones are already here.
The highest-profile announcement this year for this memory class was from Intel/Micron, on their 3D XPoint memory; this appears to be some sort of resistive random-access memory (RRAM), using “bulk properties” to provide memory storage in a cross-point layout. Both Intel and Micron predict a big future for this product; Micron claims that the 3D XPoint business could easily be of the same order of magnitude as their DRAM businesses by 2018, and Intel sees broad applications for 3D XPoint memory (dubbed Optane), and says that it will be available this year for PC and server usage.
Less noticed was a similar release from SanDisk and HP, also detailing storage-class RRAM-based memory, but with no details as to launch dates. Micron and Sony also have a jointly developed RRAM, but again no dates.
There has been a steady evolution in the image sensor biz, with Sony leading the pack, and culminating in the deep-trench isolation between pixels in the Apple 6s/6s Plus camera. Sony has had a two year+ lead in stacking the sensor on top of the image processor and connecting the two with custom TSVs, but we now see OmniVision and Samsung with design wins using multiple versions of its new stacked chip products.
We can, no doubt, expect to see a further-evolved camera chip in the iPhone 7, and Apple’s competitors will also be pushing the envelope, so we will be monitoring every new smartphone to see what appears.
Meanwhile, other sectors are developing fast – to name two, the push on automated driver self-assist (ADAS) and self-driving vehicles is providing a new space for lower-tech (but different specifications) image sensors, and security is likely to be a hot market given last year’s terror attacks.
Packaging technology has been in as much ferment as any of the wafer fab technologies, with 2.5/3D stacking getting most of the press. We expect 2016 to be a busy year in that space too; TSMC is producing its Chip-on-Wafer-on-Substrate (CoWoS) silicon interposer for a limited range of products, and seems about to launch its cheaper integrated fan-out (InFO) organic substrate, possibly using it for the Apple A10 system-on-chip (SoC) this fall.
TSMC has TSVs in volume production, though not high-density for 2.5/3D; the new fingerprint sensor in the Apple 6s/6s Plus uses TSVs so that the wire bonds don’t get in the way of the sapphire touchpad.
Intel has a parallel “Embedded Multi-die Interconnect Bridge” (EMIB) technology (to TSMC’s InFO), and given the completed Altera deal, we may finally see a 14 nm field-programmable gate array (FPGA) product with EMIB this year.
Add in the Intel/Micron HMC, SK Hynix’s HBM2 and Wide IO2 stack, and the OSATs are also pushing the envelope and likely to ship new formats this year, so there will be plenty for us to look at.
This has been a relatively high-level review of what we expect this year, but as you can see from the above, it will be quite a hectic year – lots of new technology for us to analyze!