IEDM preview: IM Flash details 25nm NAND

IEDM Previews:
Intel fabs highest mobility pFET with Ge channel
University of Tokyo first to demo III-V self-aligned source/drain
IBM, Macronix identify phase-change memory failure mode
Record photodiode quantum efficiency from Taiwan lab
How strain can protect devices from ESD
SEMATECH tipping III-V MOSFET, FinFET, and resistive RAM
TSMC anneal for gate-last HKMG process
Imec IEDM presentations to cover More than Moore, ITRS
When do TSV stresses affect device operation?
Multi-threshold-voltage flexibility in FDSOI
CMOS imager works from light to night
Carbon nanotube vias approach production densities
IBM Alliance simplifies pFET HKMG
IM Flash details 25nm NAND

by Laura Peters, contributing editor

October 18, 2010 – At the upcoming International Electron Devices Meeting (IEDM, 12/6-8 in San Francisco, CA), Intel and Micron researchers will reveal the key process advances and electrical results behind their multilevel cell (MLC), 64Gb NAND flash memory technology. At the start of 2010 their joint venture, IM Flash, said it was planning to ramp production of its 3bits/cell 64Gb NAND flash by year’s end.

In this 25nm device, aggressive scaling in both the word line and bit line directions increases word line-word line capacitance as well as cell-cell interference. Half pitches of only 24.5nm between word lines and 28.5nm between bit lines allowed a cell size of 0.0028μm2. The researchers used air gaps (see figures) to reduce total interference by 25% and bit line capacitance by 30%. They also optimized the insulating tunnel oxide and inter-poly dielectric of the cell as well as surrounding dielectric to minimize leakage and charge trapping.

Another consequence of intense scaling is the effect on dopant fluctuation. The researchers note that at 25nm, threshold voltage can be expected to vary by ~30% due to random dopant fluctuation. This is countered by additional optimization of programming algorithms to achieve multilevel cell performance comparable to previous generations including its predecessor, the 34nm 32Gb technology.

The small die size of the 64Gb NAND flash allows packaging in a standard TSOP.

NAND cell in the word line direction shows the select gate and contacts. Air gaps reduce cell-cell and word line-word-line capacitance. (Source: Micron Technology/Intel) Bitline half pitch is only 28.5nm, requiring air gaps to reduce bit line-bit line capacitance. (Source: Micron Technology/Intel)

In January, IM Flash was reportedly leading the NAND flash race with 25nm technology among contenders Samsung, Toshiba, Hynix, and others. Elpida (and Spansion) plans to start shipping samples of 1.8V 4Gb NAND flash memory during 4Q10, and will begin mass production during the first quarter of 2011.

The industry is gradually making a transition from 2-bit multilevel cell to 3-bit technology (X3). Earlier this year, SanDisk chairman/CEO Eli Harari told SST that from 2010-2013, he sees the transition from MLC to X3 for about 50% of NAND bits. For SanDisk, X3 provides more than 20% more die per wafer compared to standard MLC memory on the same technology node.


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