Tag Archives: SEMI

The Last Technology Roadmap

After many delays, the last ever International Technology Roadmap for Semiconductors (ITRS) has been published. Now that there are just a few companies remaining in the world developing new fab technologies in each of the CMOS logic and memory spaces, each leading-edge company has a secret internal roadmap and little motivation to compare directions within fiercely competitive  commercial markets. Solid State Technology Chief Editor Pete Singer covered these developments in his blog post early last year.

Rachael Courtland at IEEE Spectrum provides a great overview of the topic and interviews many of the key contributors to this last global effort. The article provides a nice graph to show how the previously predicted (in the just-prior ITRS 2013 edition) continued physical gate length reduction of CMOS transistors is now expected to stop in 2020. Henceforth, 3D stacking of transistors—perhaps built with arrays of Gate-All-Around NanoWires (GAA-NW)—will be the only way to get more density in circuitry but it will come with proportionally increasing cost.

As Gary Patton, CTO and SVP of Worldwide R&D for GlobalFoundries, mentioned during the 2016 Imec Technology Forum in Brussells, “We will continue to provide value to our customers to be able to create new products. We’re going to innovate to add value other than simple scaling.”

The 17 International Technology Working Groups (ITWGs) were replaced in 2015 by 7 Focus Teams in the last ITRS:  System Integration, Heterogeneous Integration, Heterogeneous Components, Outside System Connectivity, More Moore, Beyond CMOS and Factory Integration. The final reports from each Focus Team are available for free download from Dropbox.

The IEEE Rebooting Computing Initiative, Standards Association, and the Computer Society announced a new International Roadmap for Devices and Systems (IRDS) on 4th of May this year. Paolo Gargini is leading this work that began with the partnership between the IEEE RC initiative and the ITRS, with aspiration to build “a comprehensive end-to-end view of the computing ecosystem, including devices, components, systems, architecture, and software.”

In parallel to the IRDS efforts, the Heterogeneous Integration Roadmap activities will continue as sponsored by IEEE Components, Packaging and Manufacturing Technology Society (CPMT), SEMI  and the IEEE Electron Devices Society (EDS). Bill Bottoms is leading this collaboration with other IEEE Technical Societies that share interest in the Heterogeneous Technology Roadmap as well as to organizations outside IEEE that share this common vision for the roadmap.


3D XPoint uses PCM Material in ReRAM Device

IM Flash pre-announced “3D XPoint”(TM) memory for release later this year, and lack of details has led to widespread confusion regarding what it is. EETimes has reported that, “Chalcogenide material and an Ovonyx switch are magic parts of this technology with the original work starting back in the 1960’s,” said Guy Blalock, co-CEO of IM Flash at the 2016 Industry Strategy Symposium hosted by the SEMI trade group. However, contradicting industry terminology conventions, in another article EETimes reported that a spokesperson for Intel has said that, “3D XPoint should not be described as ReRAM.”
First promoted by the master of materials solutions-looking-for-problems Sanford Ovshinsky under the name “Ovonic” trademark, chalcogenide materials form glassy structures with meta-stable properties. With proper application of heat and electrical current, chalcogenides can be made to switch between low-resistivity crystalline and high-resistivity amorphous phases to create Phase-Change Memory (PCM) arrays in silicon circuit architectures. Chalcogenides can also function as the matrix for the diffusion of silver ions in a cross-point device architecture to create a digital “Resistive RAM” (or “ReRAM” or “RRAM”), or create an analog memristor for neuromorphic applications as explored by Prof. Kris Campbell of Boise State in collaboration with Knowm.

Hitachi and Renesas Technology developed Phase-Change Memory (PCM) cell technology employing Ta2O5 interfacial layer to enable low-power operation. (Source: Hitachi)

Hitachi and Renesas Technology developed Phase-Change Memory (PCM) cell technology employing Ta2O5 interfacial layer to enable low-power operation. (Source: Hitachi)

The Figure shows a schematic cross-section of a typical PCM cell. From a scientific perspective, we could say that any memory cell that relies upon a change in material phase to encode digital data should be termed a PCM. However, due to the history of this specific type of PCM device being the only architecture explored for decades (and commercialized for limited niche sub-markets), and due to the fundamentally different circuit architectures, it is reasonable to categorically deny that any cross-point device is a “PCM.”
However, any cross-point memory device based on a resistance change has to be a ReRAM regardless of the switching phenomenon:  phase-change, filament-growth, ion-diffusion, etc. So we could say that this new chip uses PCM material in a ReRAM device.

Electronic Materials Specifications and Markets

At SEMICON West this year, July 14-16 in San Francisco, the Chemical and Gas Manufacturers Group (CGMG) Committee of SEMI have organized an excellent program covering “Contamination Control in the Sub-20nm Era” to occur in the afternoon of the 14th as part of the free TechXPOT series. Recent high-volume manufacturing (HVM) developments have shown much tighter IC control specifications in terms of particles, metal contaminants, and organic contaminants. The session will present a comprehensive picture of how the industry value chain participants are collaborating to address contamination control challenges:
1. IDM / foundry about the evolving contamination control challenges and requirements,
2. OEM process and metrology/defect inspection tools to minimize defects, and
3. Materials and sub-component makers eliminating contaminants in the materials manufacturing, shipment, and dispensing process before they reach the wafer.

Updated reports about the markets for specialty electronic materials have recently been published by the industry analysts at TechCet, including topics such as ALD/CVD presursors, CMP consumables, general gases, PVD targets, and silicon wafers. Strategic inflection points continue to appear in different sub-markets for specialty materials, as specifications evolve to the point that a nano-revolution is needed. One example is TechCet’s recent reporting that 3M’s fixed-abrasive pad for CMP has been determined to be unable to keep up with defect demands below 20nm, and is undergoing an orderly withdrawal from the market.

As in prior years, SEMICON West includes many free and paid technology sessions and workshops, the Silicon Innovation Forum and other business events, as well as a profusion of partner events throughout the week.