Clever integration of new microelectronic/nanoelectronic technologies will continue to provide increased functionalities for modern products. Light Imaging, Detection, And Ranging (LIDAR) technology uses lasers to see though fog and darkness, and smaller less expensive LIDAR systems are needed for autonomous driving applications now being developed by dozens of major companies around the world. A significant step in the right direction has been taken by the US government’s Lawrence Livermore National Laboratory (LLNL) after working with AMFitzgerald on a MEMS mirror Light-field Directing Array (LDA) prototype.
In-process photo of the Light-field Directing Array (LDA) MEMS prototype designed by Lawrence Livermore National Laboratory. (Source: AMFitzgerald & Assoc.)
For the past several years, AMFitzgerald has been developing the fabrication process for a novel MEMS micro-mirror array designed by Dr. Robert Panas’s research group at LLNL, as shown in this video. The technology has been developed specifically to serve LIDAR, laser communications, and other demanding applications where existing MEMS mirror array technologies are insufficient. The novel design offers exceptional speed and tilt range, with three axes (tip-tilt-piston), feedback control, and 99% fill factor. The technology is available for license from the LLNL Industrial Partnerships Office.
At the upcoming MEMS & Sensors Technical Congress, on May 11, Dr. Carolyn D. White will present a case study on how she developed this complex prototype and leveraged AMFitzgerald’s ecosystem of partners to integrate specialty processes. Dr. Alissa Fitzgerald—founder and principle of AMFitzgerald leading the development of innovative MEMS and sensor solutions for specialty applications—will be giving a keynote address on “Next Generation MEMS Manufacturing” at 9:10am May 17 during The ConFab. Dr. Fitzgerald has unparalleled expertise in how to best design MEMS for different fab lines, and is a speaker not to be missed.
Currently there are eight Chinese 300mm-diameter silicon IC fabs in operation as 2016 comes to a close. Chinese IC fab capacity now accounts for approximately 7% of worldwide 300mm capacity, as reported by VLSIresearch in a recent edition of its Critical Subsystems report (https://www.vlsiresearch.com/public/csubs/). This will expand rapidly, as ten are now under construction and two more have been announced. China’s 300mm fabs are located in ten cities.
“Total Chinese capacity is expected to be around 13 million by end 2018,” said John West of VLSI Research. Worldwide 300mm wafer fabrication capacity will exceed 85 million wafers per year in 2018, putting China in control of 15% of worldwide 300mm capacity in 2018. While new Chinese fabs have yet to prove they can produce leading edge silicon ICs with high yields, it should be only a matter of time before they prove they stand among the world’s great semiconductor production regions.
West recently presented a China market outlook for semiconductors, original equipment manufacturers (OEM), and critical subsystems at the recent Critical Materials Council (CMC) Seminar (http:cmcfabs.org/seminars) held in Shanghai. At the same event, representatives from Intel and TI discussed supply-chain dynamics in China, and Secretary General Ingrid Shi of the Integrated Circuit Materials Industry Technology Innovative Alliance (ICMITIA) presented on “The China Materials Supply Consortium and China’s 5 Year Technology Plan.”
The 2016 CMC Seminar also saw a presentation of China’s first semiconductor-grade 300mm silicon wafer supplier: the recently unveiled Zing Semiconductor (www.zingsemi.com). Founder and CEO Richard Chang, co-founder of SMIC, has assembled a team and funding to start creating wafers in the Pudong region of Shanghai. He showed a photo of his company’s first 300mm silicon boule at the event.
[DISCLOSURE: Ed Korczynski is also Marketing Director for TECHCET CA, an advisor firm that administers the Critical Materials Council and CMC events.]
IM Flash pre-announced “3D XPoint”(TM) memory for release later this year, and lack of details has led to widespread confusion regarding what it is. EETimes has reported that, “Chalcogenide material and an Ovonyx switch are magic parts of this technology with the original work starting back in the 1960’s,” said Guy Blalock, co-CEO of IM Flash at the 2016 Industry Strategy Symposium hosted by the SEMI trade group. However, contradicting industry terminology conventions, in another article EETimes reported that a spokesperson for Intel has said that, “3D XPoint should not be described as ReRAM.”
First promoted by the master of materials solutions-looking-for-problems Sanford Ovshinsky under the name “Ovonic” trademark, chalcogenide materials form glassy structures with meta-stable properties. With proper application of heat and electrical current, chalcogenides can be made to switch between low-resistivity crystalline and high-resistivity amorphous phases to create Phase-Change Memory (PCM) arrays in silicon circuit architectures. Chalcogenides can also function as the matrix for the diffusion of silver ions in a cross-point device architecture to create a digital “Resistive RAM” (or “ReRAM” or “RRAM”), or create an analog memristor for neuromorphic applications as explored by Prof. Kris Campbell of Boise State in collaboration with Knowm.
Hitachi and Renesas Technology developed Phase-Change Memory (PCM) cell technology employing Ta2O5 interfacial layer to enable low-power operation. (Source: Hitachi)
The Figure shows a schematic cross-section of a typical PCM cell. From a scientific perspective, we could say that any memory cell that relies upon a change in material phase to encode digital data should be termed a PCM. However, due to the history of this specific type of PCM device being the only architecture explored for decades (and commercialized for limited niche sub-markets), and due to the fundamentally different circuit architectures, it is reasonable to categorically deny that any cross-point device is a “PCM.”
However, any cross-point memory device based on a resistance change has to be a ReRAM regardless of the switching phenomenon: phase-change, filament-growth, ion-diffusion, etc. So we could say that this new chip uses PCM material in a ReRAM device. —E.K.
As published in the journalNature, CMOS transistors have been integrated with optical-resonator circuits using complex on-chip sensors and heaters to maintain temperature to within 1°C. While lacking the laser-source, these otherwise-fully-integrated solutions demonstrate both the capability as well as the limitation of trying to integrate electronics and photonics on a single-chip. The Figure shows a simplified schematic cross-section of the device.
Full chip cross-section (not to scale) from the silicon substrate to the C4 solder balls, showing the structures of electrical transistors, waveguides, and contacted optical devices. (Source: Nature)
Lead author Chen Sun—affiliated with UC Berkeley and MIT, as well as with commercial enterprise Ayar Labs, Inc.—developed the thermal tuning circuitry, designed the memory bank, implemented the ‘glue-logic’ between various electronic components, and performed top-level assembly of electronics and photonics. The main limitation is the temperature control, since deviation by more than 1°C results in loss of coupling that otherwise provides for P2M/M2P transceivers:
* Waveguide Loss – 4.3 dB/cm,
* Tx and Rx Data Rate – 2.5 Gb/s,
* Tx Power – 0.02 pJ/bit,
* Rx Power – 0.50 pJ/bit, and
* Ring Tuning Control Power – 0.19 pJ/bit, so
* Total power consumption = 0.71 pJ/bit.
The Register reports that this prototype has a bandwidth density of 300 Gb/s per square millimetre, and needs 1.3W to shift a Tb/s straight from the die to off-chip memory. A single chip integrates >70 million transistors and 850 photonic components to provide microprocessor logic, memory, and interconnect functions.
Apple Corp. recent purchased an old 200mm-diameter silicon wafer fab in San Jose capable of creating as small as 90nm device features. Formerly owned and operated by Maxim, the US$18.2M purchase reportedly includes nearly 200 working fab tools. Some people outside the industry have speculated that Apple might use this fab to do R&D on the A10 or other advanced logic chips, but this old tool-set is completely incapable of working on <45nm device features so it’s useless for logic R&D.
As reported at EETimes, this old fab could be used for the R&D of “mixed-signal devices, MEMS and image sensors and for work on packaging.” Those who know do not speak, while those who speak do not know…I do not know so I’m free to join the public speculation. Mixed-signal and MEMS processing would require major re-tooling of the line, but this 15-20 year-old tool-set is nearly turn-key for wafer-level packaging (WLP). With minimal re-tooling, this line could produce through-silicon vias (TSV) or through-mold vias (TMV) as part of Fan-Out WLP (FO-WLP).
Our friends at ChipWorks have published a detailed tear-down analysis of the System-in-Package (SiP) used in the first generation Apple Watch; it contains 30 ICs and many discretes connected by a 4-layer printed circuit board (PCB). Significant power and performance improvements in mobile devices derive from stacking chips in such dense packages, and even greater improvements can found in replacing the PCB with a silicon interposer. With Apple pushing the limits on integrating new functionalities into all manner of mobile devices, it would be strategic to invest in WLP R&D in support of application-specific SiP design.
A secretive investment holding company out of Hong Kong named GAE Ltd has acquired 98% of the shares in Silex Microsystems AB (Jarfalla, Sweden). The transaction took place on July 13th of this year when the former major shareholders agreed to sell all of their respective holdings, while Silex founder and CEO Edvard Kalvesten retains 2% of the shares in the company and continues his role as CEO and board member of Silex. No changes are made to the organizational structure or business operations of Silex, while the new owners plan to build a new high-volume manufacturing line near Beijing that clones the equipment and processes in Sweden with first wafers out by mid-2017 (as reported at EETimes).
Silex claims to be the “world’s number one Pure Play MEMS Foundry”, has worked with AMFitzgerald&Assoc. on RocketMEMS shuttle wafers to reduce MEMS development time by 6-12 months, and has developed multiple Through-Silicon Via (TSV) technologies to allow for efficient 3D integration of MEMS and CMOS.
Almost lost as a footnote in the news is that Silex holds IP on lead-zirconium-titanate (PZT) thin-film technology that allows for efficient piezo-electric energy-harvesting chips. MicroGen Systems is currently in the market with aluminum-nitride (AlN) piezo-cantilever micro-power generator system to power IoT nodes by scavenging either single-frequency or multi-frequency vibrations, working with X-Fab in Germany as foundry partner. If PZT-based piezo-cantilever energy harvesters can compete with AlN-based devices then the former could constitute much of the product volume in the new Silex Beijing fab. In 2014, Yole Developpement forecast “the integration of IoT-dedicated electronic components to result in a market volume of 2B units for these devices by 2021;” if 30% will use energy harvesting then this represents 600M units globally.
At SEMICON West this year, July 14-16 in San Francisco, the Chemical and Gas Manufacturers Group (CGMG) Committee of SEMI have organized an excellent program covering “Contamination Control in the Sub-20nm Era” to occur in the afternoon of the 14th as part of the free TechXPOT series. Recent high-volume manufacturing (HVM) developments have shown much tighter IC control specifications in terms of particles, metal contaminants, and organic contaminants. The session will present a comprehensive picture of how the industry value chain participants are collaborating to address contamination control challenges:
1. IDM / foundry about the evolving contamination control challenges and requirements,
2. OEM process and metrology/defect inspection tools to minimize defects, and
3. Materials and sub-component makers eliminating contaminants in the materials manufacturing, shipment, and dispensing process before they reach the wafer.
Updated reports about the markets for specialty electronic materials have recently been published by the industry analysts at TechCet, including topics such as ALD/CVD presursors, CMP consumables, general gases, PVD targets, and silicon wafers. Strategic inflection points continue to appear in different sub-markets for specialty materials, as specifications evolve to the point that a nano-revolution is needed. One example is TechCet’s recent reporting that 3M’s fixed-abrasive pad for CMP has been determined to be unable to keep up with defect demands below 20nm, and is undergoing an orderly withdrawal from the market.
We’re still used to thinking that low-power chips for “mobile” or “Internet-of-Things (IoT)” applications will be battery powered…but the near ubiquity of lithium-ion cells powering batteries could be threatened by capacitors and energy-harvesting circuits connected to photovoltaic/thermoelectric/piezoelectric micro-power sources. At ISSCC2015 in San Francisco last week, there were several presentations on novel chip designs that run on mere milliWatts (µW) of power, and the most energy efficient circuit blocks now target nanoWatt (nW) levels of power consumption. Two presentations covered nW-scale microprocessor designs based on the ARM Cortex-M0+ core, and a 500nW energy-harvesting interface based on a DC-DC converter operating from 1µm available power was shown by a team from Holst Centre/imec/KU Leuven working with industrial partner OMRON.
Kudos to Dr. Larry J. Hornbeck, the extended team at Texas Instruments (TI) that has worked on Digital Micromirror Device (DMD) technology, and to the TI executives who continued to fund the R&D through years of initial investment losses. Hornbeck has been awarded an Academy Award® of Merit (Oscar® statuette) for his contribution to revolutionizing how motion pictures are created, distributed, and viewed using DMD technology (branded as the DLP® chip for DLP Cinema® display technology from TI).
The technology now powers more than eight out of 10 digital movie theatre screens globally. Produced with different resolutions and packages, DLP chips also see use in personal electronics, industrial, and automotive markets. The present good-times with DMD are enjoyed only because TI was willing to make a major long-term bet on this novel way to modulate pixel-arrays, which required building the most complex Micro-Electro-Mechanical System (MEMS) the world had ever seen.
Development of the DLP chip began in TI’s Central Research Laboratories in 1977 when Hornbeck first created an array of “deformable mirrors” controlled with analog circuits. In 1987 he invented the DMD, and TI invested in developing multiple money-losing generations of the technology over the next 12 years. Finally, in 1999 the first full-length motion picture was shown with DLP Cinema technology, and since then TI claims that the technology has been installed in more than 118,000 theaters around the globe. We understand that TI now makes a nice profit from each chip.
“It’s wonderful to be recognized by the Academy. Following the initial inventions that defined the core technology, I was fortunate to work with a team of brilliant Texas Instruments engineers to turn the first DMD into a disruptive innovation,” said Hornbeck, who has 34 U.S. patents for his groundbreaking work in DMD technology. “Clearly, the early and continuing development of innovative digital cinema technologies by the DLP Cinema team created a definitive advancement in the motion picture industry beyond anyone’s wildest dreams.”
A new silicon microstructural solution announced this month is so powerful in creating 3D patterns from 2D surface machining that I just have to share. The figure shows 3D silicon microstructures formed by compressive buckling. The method can be used to create objects with features as small as 100 nm that could be useful for developing new technologies for medicine, energy storage and even brain-like electronic networks. Note that the silicon is surface-machined using standard MEMS processes, and that all manner of silicon circuitry and thin-film sensors could be integrated into this silicon.
Colleagues from the University of Illinois at Urbana-Champaign, Northwestern University, Zhejiang University, East China University of Science and Technology, and Hanyang University created the new 2D-to-3D fabrication technique. Their trick is that after all other surface machining they chemically modify the square anchors in the surface pattern such that they are sticky. After the 2D pattern is released it is transferred onto a sheet of stretched silicone rubber. Allowing the rubber to relax back to its natural shape draws the squares toward each other, while the rest of the silicon buckles upwards. Using this type of controlled buckling, the team managed to produce a variety of elaborate 3D shapes.
The researchers even produced structures with multiple levels of elevation by designing shapes in which the relief of stress in the initial 2D shape would create further buckling, raising another part of the shape further. John Rogers of the University of Illinois at Urbana-Champaign, who is part of the micro-buckling team looks forward to an electronic cell or tissue scaffold, “A lot of the people that we talk to are enthusiastic about what you can do when you go from a passive scaffold to something that embeds full electronic functionality.”