Tag Archives: wafer

China to be 15% of World Fab Capacity by 2018

Currently there are eight Chinese 300mm-diameter silicon IC fabs in operation as 2016 comes to a close. Chinese IC fab capacity now accounts for approximately 7% of worldwide 300mm capacity, as reported by VLSIresearch in a recent edition of its Critical Subsystems report (https://www.vlsiresearch.com/public/csubs/). This will expand rapidly, as ten are now under construction and two more have been announced. China’s 300mm fabs are located in ten cities.

“Total Chinese capacity is expected to be around 13 million by end 2018,” said John West of VLSI Research. Worldwide 300mm wafer fabrication capacity will exceed 85 million wafers per year in 2018, putting China in control of 15% of worldwide 300mm capacity in 2018. While new Chinese fabs have yet to prove they can produce leading edge silicon ICs with high yields, it should be only a matter of time before they prove they stand among the world’s great semiconductor production regions.

West recently presented a China market outlook for semiconductors, original equipment manufacturers (OEM), and critical subsystems at the recent Critical Materials Council (CMC) Seminar (http:cmcfabs.org/seminars) held in Shanghai. At the same event, representatives from Intel and TI discussed supply-chain dynamics in China, and Secretary General Ingrid Shi of the Integrated Circuit Materials Industry Technology Innovative Alliance (ICMITIA) presented on “The China Materials Supply Consortium and China’s 5 Year Technology Plan.”

The 2016 CMC Seminar also saw a presentation of China’s first semiconductor-grade 300mm silicon wafer supplier:  the recently unveiled Zing Semiconductor (www.zingsemi.com). Founder and CEO Richard Chang, co-founder of SMIC, has assembled a team and funding to start creating wafers in the Pudong region of Shanghai. He showed a photo of his company’s first 300mm silicon boule at the event.

[DISCLOSURE:  Ed Korczynski is also Marketing Director for TECHCET CA, an advisor firm that administers the Critical Materials Council and CMC events.]


Apple Fab Speculation

Apple Corp. recent purchased an old 200mm-diameter silicon wafer fab in San Jose capable of creating as small as 90nm device features. Formerly owned and operated by Maxim, the US$18.2M purchase reportedly includes nearly 200 working fab tools. Some people outside the industry have speculated that Apple might use this fab to do R&D on the A10 or other advanced logic chips, but this old tool-set is completely incapable of working on <45nm device features so it’s useless for logic R&D.

As reported at EETimes, this old fab could be used for the R&D of “mixed-signal devices, MEMS and image sensors and for work on packaging.” Those who know do not speak, while those who speak do not know…I do not know so I’m free to join the public speculation. Mixed-signal and MEMS processing would require major re-tooling of the line, but this 15-20 year-old tool-set is nearly turn-key for wafer-level packaging (WLP). With minimal re-tooling, this line could produce through-silicon vias (TSV) or through-mold vias (TMV) as part of Fan-Out WLP (FO-WLP).

Our friends at ChipWorks have published a detailed tear-down analysis of the System-in-Package (SiP) used in the first generation Apple Watch; it contains 30 ICs and many discretes connected by a 4-layer printed circuit board (PCB). Significant power and performance improvements in mobile devices derive from stacking chips in such dense packages, and even greater improvements can found in replacing the PCB with a silicon interposer. With Apple pushing the limits on integrating new functionalities into all manner of mobile devices, it would be strategic to invest in WLP R&D in support of application-specific SiP design.