EUVL Focus

2017 SPIE Advanced Lithography – EUVL Conference Update

By Vivek Bakshi, EUV Litho, Inc.

To simplify the vast amount of information from the 2017 SPIE AL EUVL Conference for my blog, I have adopted a new format. It includes a short summary of EUVL Status, a list of notable updates, and additions to the current list of EUVL Challenges (previously published on this site). An additional commentary will follow this blog.

  1. Current EUVL Status 

Source: Current power of 148 W corresponding to 104 wafers per hour (WPH) scanner throughput in-house at ASML. Stable 130 W noted in field. 375 W in lab EUV sources in burst mode at 50 KHz. 200 W of stable power is possible in field in 2017. Source power now meeting requirements for introduction of NXE3400. Current source availability at 75%, needed at >90%. Droplet generators and collector lifetime improving but need further improvement.

Scanners: Fourteen EUVL scanners in field. Four shipped in 2016. 0.3 nm critical dimension uniformity (CDU) and 1.8 nm overlay. 148 W and 104 WPH with increase of 8 wafers per hour (WPH) achieved via increase of stage speed at the same source power.

Masks: Mask blank defects acceptable for now via defect avoidance and repair.

Mask Pellicles: Mask defect addition during manufacturing is still a concern for chip makers. Pellicles are at 125 W and need to be ready for 250 W by 2H 2017. 

Mask Defect Inspection: Samsung has made its own AIMS tool and plans to use it for high volume manufacturing (HVM). Tool is using HHG based EUV source and a scanning zone plate. Zeiss is now shipping its first AIMS tool. Actinic Patterned Mask Inspection (APMI) tool still missing. Mask defect inspection via wafer inspection for now, at a cost and with lower yield. APMI is only red flag item for 7 nm insertion of EUVL. 

Resist: Lots of talk about stochastics, but I believe it will be addressed and it is not a showstopper. Important to note that resist image is only an intermediate step and there are still several knobs available to improve the performance of the final circuit – which is what matters.

  1. Notable Updates 

Scanner and imaging

  • Increase of throughput by 8 WPH via greater stage speeds is first such increase, with more to come. Now expect source power of 210 W to give 125 WPH instead of 250 W (increase in throughput via stage speed improvement)
  • Extension of EUVL to low k1 may be more difficult than for 193i. Discussion of various factors and how to address them has started.
  • More enthusiasm for high NA scanner, as it can help with line width roughness (LWR) and extension to lower k1. Detailed checklist of High NA challenges from Samsung.
  • Data showing that around 5 sigma errors deviate from standard distribution. We do not understand error distribution behavior at 5 to 7 sigma (it is no longer a normal distribution). We now need to print one trillion vias in one exposure with no open! 3 sigma is no longer enough.
  • Closer cooperation among litho, etch and deposition is the way to reduce EPE and address stochastics. Work has already started.
  • Scanner to scanner variation higher for EUVL than for 193i. How to address this in optical proximity correction (OPC)? Will this lead to scanner specific EUV masks?


  • Need to better understand source power requirements for 3 nm and beyond. How much additional help we will get from scanner for increasing throughput? Is 500 W enough? Will we need additional power?
  • Power scaling to 500 W is still lots of work and not a done deal as conversion efficiency decreases at higher pulse energy (favored method for power scaling). 


  • Introduction at 7 nm planned at 20 mJ dose
  • Micro bridging (aka nano bridging) of resist is a new challenge reported by several people. Its relationship to dose, type of resist and LWR is not clear. Some said that this may become bigger than LWR issue. Papers showing OPC and Litho- etch optimization can help reduce this effect.
  • Continued work on chemically amplified resists (CAR), metal based inorganic resists and molecular resists to support 7 nm and beyond.
  • Out of Band (OOB) filter in now in scanner that also acts to keep resist outgassing products out.
  • Sigma alone may be insufficient to characterize LWR. New additional variables needed? 


  • Replacement of current mask absorbers by Ni to improve imaging. Continued review of new mask structures with improved imaging potential, but patterning challenges exist for these new stacks.
  • Need source mask optimization to address 3D mask effects.
  • High sensitivity to Pellicles defects for small pupil fills imaging
  • Need for further analysis and reduction of defects in the scanner, that end up on masks, generated during manufacturing.
  • Current fixed pellicle design needs to evolve to provide future solutions.
  • New carbon nanotube based pellicles from IMEC
  • New APMI design from PSI/ETH, supported by small synchrotron based EUV source.

New terms heard at SPIE AL

  • Etch Color, CD healing, Black Swans (at seven sigma), Vote-taking Lithography (resurrection of a 1986 idea to move away from 100% defect free mask requirements), nano bridging and micro bridging of resists, and Tone inversion.

Most Interesting Papers

  • Couple of papers on stochastics – Line edge roughness (LER) performance targets for EUVL (10143-10) by Tim Brunner of GlobalFoundries and Lithographic Stochastics – extrapolating to 7 sigma (10143-31) by Robert Bristol of Intel.
  1. Additions to existing list of challenges for EUVL

7 nm

Nothing new

5 nm

Micro bridging of resists

Error distribution at 5-7 sigma 

3 nm

Power scaling to 500 W and beyond

Micro bridging of resists

Error distribution at 5-7 sigma

Areas of Focus and List of Challenges for EUV Lithography at 7nm, 5nm and 3nm Nodes

By Vivek Bakshi, EUV Litho, Inc.

As we look forward to 2017 SPIE Advanced Lithography Conference in San Jose next week, the focus once again will be on EUV Lithography, its readiness for manufacturing and plans of chip makers for starting to use EUVL in their fabs.

Insertion is planned from 7 to 5nm nodes by chip makers in coming years. The areas of focus at 7nm are mostly related to productivity and uptime goals of sources in addition to pellicle. The 5nm insertion has few other areas come into focus where more work is needed like actinic inspection, resist readiness and mask blank defectivity – although none of them is a showstopper.

List of challenges pick up lot more at 3nm node, as we consider high NA scanner, corresponding newer design for EUV masks and need to for upto 500 W of source power. A detailed list of these challenges is worth a review and is now published at the website as topics for 2017 EUVL Workshop in June 2017. I will be updating this list after as well as sharing my opinion on the latest with EUVL in coming weeks after this year’s SPIE AL meeting.

Bringing you Holiday Cheers – Courtesy of Moore’s Law

Vivek Bakshi, EUV Litho, Inc.

Author’s preface: This article is a departure from my usual high-tech language, because I think our industry needs to do more to educate non-technical readers about how their treasured electronic devices got to be so cheap and powerful. Our success in realizing Moore’s Law has been one of the greatest achievements in modern science, and we must continue doing all we can to continue that progress. Please feel free to share this essay as a holiday gift to anyone in your life who benefits from the achievements of lithography.

For many, our Christmas holiday cheer is wrapped around getting the latest gadget that brings us more power to do things than we had the year before ‒ be it a new iPhone, iPad, laptop or some other high-tech gizmo. Added to this annual ritual, which we now intuitively expect but do not quite notice, is that we pay less or the same for these gadgets than we did in previous years – even though they may run twice as fast and store three times as many photos and videos. At the heart of this happy surge are the computer chips that grow more powerful every year without increasing their price. I would like to tell you how we in the computer chip industry do this, and what it will take to continue this trend in the coming decades.

Technology was not always like this. Growing up in the early 80s in India, where my dad worked for the telephone company, I remember that when we got a new phone it was the same rotary dial model with just a new exterior body, and maybe a new color. If today’s technology were moving at the same speed as then, we would only be getting a new cover for our iPhone or a new computer mouse for Christmas, and not more powerful gadgets.

To understand this phenomenon, we need to look at the leading-edge computer chips that are the heart of all these tools, made by leading chipmakers like Intel, Samsung and others. Inside these microchips are tiny transistors and other circuit elements that do the work. The reason these devices can deliver more power every year at lower cost is because the advancement of computer technology is guided by Moore’s Law, named after Gordon Moore, co-founder of Intel Corporation. Moore proposed this law in 1965, saying that number of transistors per square inch would double every two years or so.

We have been able to follow Moore’s Law so far by making transistors and other circuit elements smaller every year. Making computer chips takes many steps, the most critical of which are embodied in a process called Lithography, which involves printing the images of circuits. To print smaller and smaller transistors, we need to be able to resolve the printed images. British physicist Lord Rayleigh (1842-1919) pointed us to “knobs” that we can turn to resolve ever-smaller images. Prominent knobs are color of the light for printing (wavelength), design of optics (numerical aperture) and printing under something more dense, like water. We also have also learned lots of tricks (called optical proximity corrections and multiple patterning) that let us keep on printing smaller and smaller features.

The current technology of choice for advanced printing of computer chips is called 193 nm optical projection lithography, which involves a zillion optical tricks and repeats the printing process three or four times to make one image. However, 193 nm has been running out of steam for some time. This means that either we cannot make computer chips more powerful by just shrinking the size of features, or the cost of doing so will be a lot more. Neither of these are acceptable solutions, and that is where Extreme Ultraviolet Lithography (EUVL) comes into play.

EUVL promises to extend Moore’s Law by changing the color of light used for printing – from current 193 nm light from excimer lasers to 13.5 nm light from plasma sources. Alas, we cannot see either wavelength with our unaided eyes. This switch of color came with big physics challenges as EUV Light, with its photons of 14x energy, interacts with matter very differently than photons from excimer light. This change has resulted in a massive amount of work over many decades on light sources, optics and photo-sensitive chemicals for developing images. For these reasons, EUVL has taken many decades of worldwide effort and investment and is now expected to be used by leading chipmakers by 2018- 2020 time frame.

We would certainly be lost without the ever-more powerful computer chips that we are now used to having at our disposal every year. So now you know whom to thank for your new holiday gadgets, and you can rest assured that they will keep on working to ensure the benefits of Moore’s Law will continue for years to come.

Highlights from 2016 EUV Source Workshop – Work on Conversion Efficiency of EUV Sources and Continued Progress in Source Technology

By Vivek Bakshi, EUV Litho, Inc.

The 2016 Source Workshop was held Nov 7-9, 2016 at ARCNL, Amsterdam, The Netherlands. During the workshop we received new information about EUV source power, updating what we learned at the EUVL Workshop in June. ASML now has 125 W sources in field with their uptime improving, and 210 W dose controlled sources in lab, with 5.5 % conversion efficiency (CE). This leads me to predict that we will be able to have 250 W in field by 2018, which will be needed to support manufacturing at 125 wafers per hour. Another piece of good news on the high power source front is the continued solid progress by the second-largest supplier of HVM EUV sources, Gigaphoton. They now have 100 W @ 5% CE, with 95% duty cycle for 5 hours of continuous operation.

There were reports of continued progress on EUV metrology sources, but they are still years away from being integrated into the next generation of mask defect inspection tools. In the workshop, I heard that Zeiss is now working closely with suppliers to evaluate their EUV metrology sources for their next generation AIMS tool. We also need patterned mask inspection (PMI) tools to be ready sooner than later, and I was happy to see a presentation by KT on the status of the source for their PMI tool. However, when and if this tool will become reality is still unknown, while these tools will be needed at 5 nm application of EUVL in fabs.

This year there were several papers (experimental and theoretical) on how to increase CE of sources by looking deeper into the working of EUV sources. In EUV sources, the laser energy (which is at 10 micron wavelength) is converted into 13.5 nm photon. Current reported CE is 5.5 to 6%. Can we can get more efficient?

We learned, via plasma measurements, how we can better tweak the delay and shape of laser pre-pulses (Kyushu University papers) and were told about development of pre-pulse lasers to enable the delivery of those optimum pulses (work from HiLase).

I found interesting the work of Hanneke Gelderblom, Univ. of Twente and Dmitry Kurilovich, ARCNL. They are using “water drops as scale model for tin” to understand the scalability of hydrodynamic stability of droplets interacting with lasers. They found that they can adjust parameters to work in regions to avoid drop breakups during interaction of laser with droplets, while looking for greater laser absorption to increase CE. It was a good example of how we can use learnings from other disciplines to improve the functionality of EUV sources.

Gerry O’Sullivan of UCD pointed to the need for maximizing the line emission by reducing opacity and reducing recombination. He noted that plasma density has a “sweet spot” for a maximum CE and optimized CE. He also described his wedged target colliding plasma that can be better matched to CO2 for increasing CE.

A most interesting CE paper to me was one by Mikhail Basko. He pointed out that in principal, 20% CE is possible (based on 40% spectral efficiency calculations) but in reality only 9% CE can be achieved. He pointed that 2.5% of CE is lost as the kinetic energy of plasma flow, while rest of CE is dissipated due to non-uniformity of temperature across the “working” zone and in-band reabsorption. We need to find ways to achieve this optimum density profile in our tin targets to get to 9%.

There were several interesting papers on modeling efforts to improve CE (LLNL, ISAN, Cymer) and generation of fundamental data to improve modeling. Such efforts are going to be important as we run out of knobs readily available to us today to improve CE, and we must look deeper into the working of plasma sources to squeeze those additional EUV photons out of plasma and search for stable operational modes for sources that can be sustained in factories around the clock.

We had many excellent papers on XUV sources and their applications to support manufacturing in the semiconductor industry and beyond. Hans Hertz in his keynote speech described his water window microscope, which with a 200 W laser of 600 picosecond pulse operating at 2 kHz gives an early synchrotron level of brightness. It can now do 3D tomography with a 10s exposure. These developments were possible due to a new multilayer mirror with >4% reflectivity (optiXfab) at water window wavelengths. He had reported the development of these new multilayer mirrors in last year’s source workshop, and decided to incorporate them in his tool to achieve this progress.

This year’s workshop had the highest attendance ever. I was happy to see continued work by the research community and suppliers to better understand the working of EUV sources, so that we can achieve those 500+ W sources that can operate 24/7 in fabs with 80-90% uptime.

Pushing Frontiers of EUV Source Technology – 2016 Source Workshop (November 7-9, 2016)

By Vivek Bakshi, EUV Litho, Inc.

EUV Sources remain the key component for ensuring EUV Lithography’s entry into fabs for high-volume manufacturing. Two big factors that have enabled dramatic progress in source readiness are related to improvements in source power and source lifetime. Now the question is how far we can push source power and lifetime, and what is needed to enable continued progress.

For answers, we need to look into the fundamentals of plasma based EUV sources, as well new engineering designs. The present conversion efficiency (CE) of sources is a couple of percent, while the theoretical maximum approaches 8%. If we are at 2.5% CE today, it means we can get ~ 3 times more EUV photons from the same level of energy input, if sources could be operated closer to 8% CE. The lifetime (optics and fuel delivery system) also needs to be such that 90% uptime goals of tools can be met.

During the upcoming 2016 Source Workshop, we will have papers taking a closer look at these topics. There are several papers on how to increase the CE of sources to allow us to get more source power. There will be another session on plasma dynamics of EUV source to further our understanding and enable newer designs of sources that will help bring about better CE and longer source lifetimes.

Another important topic is EUV sources for metrology. Low power but brighter EUV sources than those available today are needed for actinic inspection of masks. We will have new potential designs from five suppliers for actinic EUV sources, as well as papers on high harmonic generation (HHG) and free electron laser (FEL) based sources for EUVL. In addition, we will have sessions on XUV sources and their application in patterning and other industrial application like water window microscopy.

I look forward to these new ideas and updates in the EUV and XUV source technology area. The Source Workshop this year is in Amsterdam, The Netherlands, held in conjunction with ARCNL. Dates are November 7-9, 2016 and additional information is available at

Update from EUVL Workshop in Berkeley

By Vivek Bakshi, EUV Litho, Inc.

The 2016 EUVL Workshop was held last month at LBL in Berkeley, where we heard the latest news on EUV Lithography R&D development topics. The keynote talks were given Harry Levinson (GlobalFoundries), Britt Turkot (Intel) and Igor Fomenkov (Cymer/ASML). There were progress reports on the current technical areas of focus that I will talk about below. However, I would like to point out first that since the Workshop ended, both TSMC and Samsung have announced plans to use EUV Lithography in production at the 7 to 5 nm node. Both expect to receive the NXE3400 production-level EUVL scanner during the first half of next year, which they will adapt for 7 nm node products. This speaks for itself in terms of EUVL readiness for production.

EUV source power continues to make progress, with meaningful demonstration of >200 W by both Cymer (an ASML company) and Gigaphoton. Both suppliers now think that 500 W EUV power is feasible. Not long ago, sources appeared to be the main obstacle to the introduction of EUVL into commercial production. However, presenters from Cymer (Igor Fomenkov) and Gigaphoton (Hakaru Mizoguchi) convinced me that 250 W (and hopefully 500 W) are achievable. For this reason, both Igor and Mizoguchi-san deserve to be called the “Saviors of EUVL.” Of course, they each represent a large group of multi-disciplinary teams, who have achieved a goal that many thought impossible. True, sources still need to meet operational cost and uptime goals in order to satisfy manufacturing requirements. However, steady progress is being made on this front, as pointed out by Intel in their keynote talk. I also expect 200+ W to be achieved in fabs sometime in 2017.

Although chip makers have figured out how to live with mask defects for now via defect avoidance and repairs, mask defect reduction is certainly on the wish list. Patterned mask defect inspection (PMI) is being done in different ways, with wafer inspection being one of them. Alternate PMI techniques were discussed in the presentations as well during the Workshop. Lack of a specific PMI tool remains a key issue for cost-effective, EUVL based manufacturing. I believe that lack of commercial metrology EUV sources that meet brightness requirements to support PMI and other actinic inspection tools remains a big gap, but no one seems to be coming forward and addressing this deficiency. We know we need it, so why not work on it? It is going to get more expensive without a PMI tool and other inspection tools with low throughput in the absence of a bright EUV metrology source.

Pellicles to protect masks can now withstand 125 W of thermal load, with 250 W as the present goal. I see progress, but we are not at 250 W yet.

The Industry is finally realizing that in order to make substantial progress in developing EUV resists, we need to get back to basics and better understand how they work. As EUV resists operate differently than 193 nm resists (via secondary electrons), there’s a lot that we still need to understand. There was a good set of papers on this topic, led by Frank Ogletree of LBL and others. I certainly hope that we will see lots of industry support for his work, as the return on investment on such basic research is sure to be huge.

The Workshop was moved to CXRO, LBL in Berkeley, CA this year. This year’s Workshop, the ninth to date, was the best- attended yet and offered the most papers ever. Participants found the new location very convenient with regard to travel logistics and access to area colleagues working on EUVL. CXRO continues to be a leader in EUVL R&D and has recently announced a new consortium, EUREKA, that will support continued EUVL development.

The Workshop proceedings can be downloaded at

Latest on EUVL Development to be Discussed in EUVL Workshop in Berkeley

By Vivek Bakshi, EUV Litho, Inc.

During this year’s SPIE Advanced Lithography conference in San Jose, there was a definite switch to optimism about EUVL from all keynote speakers. The message of “Not if, but when” for EUVL ‒ with early adoption expected in coming years ‒ was clearly heard from leading-edge chip makers and EUVL suppliers. With demonstration of 200 W source in the lab and steady progress on source power and availability, the focus has now shifted to fab productivity, mask, pellicles and resists.

This year’s 2016 EUVL Workshop is being held in Berkeley, CA, organized in cooperation with CXRO. With keynotes from Intel, GlobalFoundries and ASML, along with 45 speakers and about 50 papers, we expect to hear a good bit of new information on these topics and stimulating discussion of R&D topics. In addition, we will hear about alternate actinic inspection techniques and fundamentals of EUV resists. For EUV resist, where the chemistry is dominated by secondary electrons, researchers are looking into understanding chemical reactions in this new realm to develop resists that pattern better at EUV wavelengths.

I am looking forward to finding out the latest on EUVL in this workshop. The final agenda and abstract book is available at

2015 Source Workshop – What we expect to hear

By Vivek Bakshi, EUV Litho, Inc.

EUV Sources remain the key enabler to move EUVL into manufacturing, and we look forward to the upcoming 2015 Source Workshop (November 9-11, 2015, Dublin, Ireland) for the latest developments and status of EUV Source technology. Both high-volume manufacturing (HVM) level and metrology EUV sources are needed for chip manufacturing using EUVL. For HVM sources, power level and availability are needed to generate cost effective throughput.

We expect to hear from the user (Intel) as well as source makers (ASML and Gigaphoton) on the latest performance of these sources. At last summer’s 2015 EUVL Workshop we learned that 80 W sources are in the field, but availability needs to improve. So we look forward to finding out the latest performance results from users and suppliers. We will also have a session of FEL-based EUV sources in this workshop. FEL is currently being explored as a technology option for 1000 W and higher EUV sources.

Metrology sources are equally important as they support mask defect metrology tools. Our agenda includes all current EUV metrology source suppliers as well as most research organizations that are working to develop these types of sources. For metrology sources, brightness, stability and source availability are the key matrix of performance.

2015 EUVL Workshop Update

I usually take a week or two to summarize the workshops that I organize or attend, as I am not a reporter but more of an analyst. However, I did not get to report on the highlights from the EUVL Workshop, as I was out on paternity leave. However, proceedings were made available after the workshop, as always.

Although much interest has been shown over the last year in the high absorbing EUV resists – which can reduce the source power requirements for HVM scanner – we learned in the 2015 EUVL Workshop that they are not ready (and may not be ready for many years to come) for commercial use. Hence, the pressure remains for source power scaling, as it will continue to be primary enabler of increased throughput in the near future.

Earlier this year, KLA-Tencor put the patterned mask defect metrology development on the back burner. We need this mask defect metrology tool for patterned wafers for manufacturing via EUVL. Hopefully, their planned merger with LAM will revitalize this program. In any case, the performance (throughput) of this and other mask defect metrology tools still depends on the metrology sources. We expect to hear about the status of these sources in the 2015 Source Workshop.

EUV Lithography – What is Next and When?

By Vivek Bakshi, EUV Litho, Inc.

This year started with an announcement, during the SPIE AL Conference, of the achievement of 100 W+ power from high volume manufacturing (HVM) EUV sources in the fab. One hundred watts at intermediate focus has been a long-standing benchmark and is a definite success, and we also can be sure that source power and availability will increase this year. The focus will now change to addressing the remaining challenges of EUVL, with questions turning on what comes next and when, as the industry prepares to deploy EUVL into HVM.

During the 2015 EUVL Workshop (June 15-19, 2015), we expect to get answers to these questions in the various keynote and invited talks. And to make sure the best information is available, we are also having a panel discussion that will address the following questions:

1. When do you expect the industry to insert EUVL into high volume manufacturing (year and process node)?

2. What are the top three challenges (technical and business) that need to be addressed to ensure readiness of EUVL for HVM? (Some examples of technical challenges are source power and availability, pellicles, mask inspection infrastructure and high absorption resists. An example of a business challenge is readiness of PMI tools.)

3. How will the industry achieve the following targets for EUV Source power: 250 W, 500 W and 1000 W?

4. When do you think that HVM worthy EUV resists with sensitivity of <5 mJ will be ready?

5. For extension of EUVL to smaller nodes, what are the pros and cons of High NA vs. Double Patterning?

6. If the industry had to start all over again to develop EUVL for HVM, what are the top three things you think should be done differently?

We hope you will join us in the Workshop as experts present their responses on these topics and answer  questions from the audience. More information on the Workshop, including the agenda and abstract book, is available on our website

The EUVL Workshop will be relocated from Maui to the U.S. mainland in 2016.

2015 SPIE Advanced Lithography EUVL Conference – Summary and Analysis

By Vivek Bakshi, EUV Litho, Inc.

The SPIE AL EUVL Conference was held from February 22-26, 2015 in San Jose, CA. The atmosphere in this year’s EUVL Conference was the most positive toward EUVL that I have ever seen.  Here, in this blog, I will summarize the papers and data that caught my attention, give my opinion on the latest status of EUVL, and list the challenges that are still to be addressed.

Scanner status

TSMC presented data on the latest NXE 3300B EUVL scanner. With an 80 watt EUV source, the scanner ran continuously for over 24 hours and processed more than 1000 Wafers in one day. These results are a dramatic improvement from last year, when TSMC complained about not being able to break the 10W source power barrier. Machine to machine overlay and mix and match overlay (with immersion tools) continue to improve for these scanners. TSMC also showed line and space with 15 nm half pitch and 14nm trenches. Field data from IBM for 3300B showed that optics maintains up to 90% cleanliness for six months or for 50 gigapulses. The availability of EUVL scanners is now >55% and continues to increase. ASML, in their review of status, pointed out that 3300B scanners now meet the patterning requirement for the 7nm logic node and 15nm DRAM node.

Hynix in their talk also discussed a three-day continuous run with their 3300B scanner, during which they exposed 99.85% of wafer dies on 1,670 wafers with +/- 1% dose error. This shows continued growth in the maturity of EUV scanners. Hynix claimed they can now use EUVL scanners with “sufficient productivity with better or comparable yield” compared to immersion scanners.

EUV mask Pellicle

The industry now plans to use pellicles to protect the EUV mask from defects added during manufacturing. Full size pellicles with 85% single pass transmission (30% total loss) are now manufactured by ASML and the transmission is supposed to increase to 90% this year (20% total loss). One of the impressive parts of this technology is that these pellicles can now be shipped worldwide without breakage – as I remember that damage from broken pellicles was a concern when they were first proposed. In a video demonstration, ASML showed technicians dropping a box containing the pellicles without damaging them.  Another new invention reported during the conference was that EUV pellicles can now be easily removed to allow non-actinic inspection of masks, if so desired. ASML pellicles also do not interfere with imaging as they have a negligible effect on CD uniformity (CDU) and line edge roughness (LER). Hanyang University had a paper that showed alternate material choices for EUV pellicles, which have potential for higher transmission and larger reflection of out of band (OOB) radiation.

High NA Scanner and optics

Optics quality (wave front error and flare), scanner optics throughput, and illumination schemes continue to improve and credit goes to Carl Zeiss. Numerical aperture (NA) for scanners needs to increase in order to further increase resolution – ASML has 0.5 NA on their roadmap for resolution beyond 10nm HP. Until last year, high NA options for scanners included an increase of mask size to 9” and/or a decrease in throughput. None of these options seemed to be agreeable to all parties (mask makers or chip makers). However, since then a new design called “anamorphic optics” has been proposed by ASML and Zeiss. This will have 8x magnification in the scan direction and 4x magnification in the other direction, as normalized image log slope (NILS), with a target of 2, needs to improve for horizontal lines only. There were several papers on anamorphic optics – mask design to simulation of optical performance. As this option will pattern only half field, ASML had proposed solutions to compensate for throughput loss: increase in speed  of reticle stage, deployment of central obscuration in the illuminator and increase in the average reflectivity of mirrors (via narrowing the angles in the optics).  It was also pointed out in a paper that 4x by 8x  magnification at half field offers a process window similar to what we can get from straight 8x quarter field magnification. Based on this data, it looks to me like this new optics design will be adopted by the industry for high NA EUVL scanners. (I only wish the increase in throughput options via greater stage speed and improved optics had been adopted earlier to give a boost to the throughput of current 0.33 NA tools!) It was also mentioned that high NA tools will allow scaling to two additional nodes beyond 10nm resolution, instead of needing to move to multiple patterning.

EUV Source

The best paper of the conference (in my opinion) was from Alexander Schafgans of Cymer, as he explained in detail information about the performance of shipped, in-development and planned EUV sources from Cymer. This was new information not shared publically before. The extinction of pedestal in CO2 laser pulse was the main reason for the increase in the power from 30 to 80W. Today, Cymer has an in-house 100 W source which operates with 3.5 % conversion efficiency (CE), 15 kW drive laser and 17% overhead cost (meaning only 87% of the light output is used to ensure required dose control). With a master oscillatory power amplifier (MOPA) and pre-pulse based system, they eventually hope to get 5.5 % CE with a 27 kW CO2 drive laser. If there is no additional factor that lowers the performance of source, this proposed switch should give them a factor of 2.6 over current source power or ~ target of 250W. However, based on current field data, I expect only 125 W to be reliably available in field this year. I am not quite ready to support prospects of reliable 250W by the end of this year, although this power level now seems to be feasible in the near future.

Gigaphoton, the other high power source maker, issued a press release before the symposium announcing 142W at 50% duty cycle (71 W average power). This source operated at 4.2 % CE and 70 KHZ in a burst mode for a short time. In December of last year, they also achieved 120 W at 50 % duty cycle for 2 hours. They now have ~15 days availability of debris mitigation scheme and their approach is to obtain 250W in burst mode first and then work on improving the source availability.

Free Electron Laser (FEL) based EUV Sources

I did not see any plans from LPP based source suppliers (Cymer and Gigaphoton) to scale the power beyond 500W range, and now the industry is increasingly focusing on FEL based EUV sources for higher power options of 500- 1000W, which will be needed for high NA scanners.  Erik Hosler of GlobalFoundries gave an overview of various technical options for developing an FEL prototype. I would like to see more papers and discussions on this topic, and so I am organizing a special session on FEL based sources in the upcoming 2015 EUVL workshop.

EUV Resists

The most important news about EUV resists came from a side meeting during the conference that I could not attend. Due to strict outgassing requirements, put in place to protect the scanner optics, it takes a long lead time to get a new EUV resist approved to be evaluated in the EUVL scanner. These outgassing testing requirements are now gone for chemically amplified resists (CAR), as most EUV CAR have been passing the requirements and hence the outgassing test is not critical. For other non-CAR chemistries, up to 100 wafers can be processed in the EUVL scanner before needing outgas testing certificate to continue. This change in requirements ought to drastically increase the number of new chemistries that are being tested for performance, speeding up EUV resist development. In any case, I will assume that outgassing tests will still take place for the few selected CAR candidates for high volume production and for promising new non-CAR chemistries. I would also like to point that there is now lot more focus on negative-tone CAR resists for EUV for meeting the resist requirements.

Intel had a nice paper giving the status of high absorbing EUV resists based on metal oxides, when used in a production environment. The current commercial HfO2 based resist show a shelf life of three to four weeks only, which needs to improve. The patterning performance of these results needs to progress as well, as these resists also have an issue with contrast, and demonstrated scumming and pattern collapse. Intel is currently working on a dry develop process to improve the performance of these resists.

I had been waiting to hear about these metal oxide based EUV resists, as due to high absorption property, they can dramatically reduce EUV dose requirements and hence relax source power requirements. However, it looks like they are not quite ready for production and some people pointed out to me during the conference that it can take three to five years to get a resist ready for high volume production. In a later paper in the same session, Chris Ober of Cornell University showed data on high sensitivity HfO2 (2.2 mJ) and ZrO2 (1.8 mJ) resists, but both resists had LER of ~ 6nm. In an EIDEC paper, I also noted 1.5 mJ resists but LER appeared to be high, although numbers were not given. Chris Ober also pointed out that the nano-aspect of these metal resists does not make it more toxic and these resists have passed outgassing tests at IMEC. Commenting on the Intel paper, presented by one of his ex‑students, he thinks he has some ideas to address the shelf life issue. I also hope that LER requirements will be met, as they are critical for acceptance of a resist for production.

EUV Masks

Although mask defectivity continues to drop, as shown for Hoya mask blanks by TSMC, more work is needed to reach acceptable mask blank defect levels. Patrick Kearney of SEMATECH presented a paper on the use of magnetron, instead of current ion-beam deposition (IBD) technology, to produce mask blanks. The magnetron technology, although still behind IBD in terms of defectivity, provides better reflectivity and better manufacturability. Also, mask pattern shift is the method that is increasingly being employed to reduce defects in patterned masks.

Obert Wood of GlobalFoundries presented a paper on alternate multilayer materials for masks to support higher NA scanners (Ru/Si multilayer with carbon interlayer instead of Mo/Si), which will allow less shadowing and hence smaller through-focus pattern placement errors. The topic of alternate materials for masks was again brought up in the mask topography session in papers from EPFL (Switzerland) and TSMC, showing improved imaging results via using alternate buffer layer materials.

Pei-Yang Yan of Intel talked about her work on reducing the contribution of mask-related LER to the final images. She is now able to get mask roughness down to 47 pm, which contributes only 0.3 to 0.7nm LER to images.

Mask Defect Inspection

Carl Zeiss plans to deliver an AIMS tool in Q4 of 2015 to support mask defect repair, and chip makers are discovering alternate ways to find defects on patterned mask, while an actinic patterned mask defect inspection tool is not available. However, I was happy to hear that KLA-Tencor will have a paper in the upcoming 2015 EUVL Workshop on the status of their actinic inspection tool – as actinic inspection is needed for the shift to high volume manufacturing. Despite a rumor that a high throughput e-beam inspection tool will be presented in the conference, which when combined with a removal EUV mask pellicle would eliminate the need for actinic inspection of patterned EUV masks, I did not hear of such an announcement. So if I missed this news, maybe someone can update me. Even with a pellicle, EUV patterned masks may still have defects that are generated during production from handling, or from contamination trapped between masks and pellicles. Although existence and frequency of these defects has still not been proven, chip makers will prefer to have a through pellicle actinic inspection for patterned EUV masks.

There was also a very nice presentation from Ken Goldberg of LBNL, giving an overview of the SHARP microscope, a tool being used by chip makers to actinically review EUV mask defects. Such projects highlight the value of technology and the skill set available at national labs to support the development of EUVL.

So When EUVL Will Reach HVM?

I had a lunch with a business analyst, who viewed EUVL and this whole debate on NGL as one of the greatest technical challenges of our time. I agree. To him and some readers of my blog, the key question is when will EUVL be used in high-volume production. Per the ASML roadmap, the throughput of NXE3350 at 125 W is ~ 75 Wafers per hour (WPH), and with two 3300Bs being upgraded to 3350 levels and two new 3350 scanners operational at TSMC this year, TSMC can hope for throughput  ~ 300 WPH later this year from their four NXE3350 EUVL scanners.  As source power climbs to 250W in these scanners, throughput per scanner will climb to 125 WPH, or 500 WPH for four scanners. These throughput numbers indicate the capability for moving beyond mere product development. Unfortunately, we will know that EUVL is coming to HVM for sure only when it is announced by one of the leading edge chip makers – GlobalFoundries, Hynix, Intel, Samsung, Toshiba, or TSMC. I am expecting to hear such news in 2016 or at the latest 2017, when topics such as source availability, resist readiness and actinic inspection have been addressed.

Zen and the Art of Technology Development

This winter my favorite Zen teacher is teaching a course on the topic of “Faces of Compassion – Vows of Bodhisattvas.” I learned that Bodhisattvas (beings spiritually advanced but not yet enlightened) reflect the deepest part of ourselves. When we are working in our daily lives (developing new technology which may be a better EUV source or something else) we are living our “vows” and that is how we serve others and ultimately ourselves. I mention this as I see similarities between the fundamentals of technical development and the principles of vows of Bodhisattvas. Computer chips and their manifestations as iPhones or laptops or routers or servers are driving the leading edge of what we humans do today in war or in peace, and what we do is embodied in the “vows” we undertake to serve. Our introspection combined with a global view will reveal the way forward.

Quoting Zen teacher John Tarrant:

“The journey of Buddha isn’t a literal journey that happened long ago… It is here now and paying attention helps you notice that. If you look into the life you have, your looking will lead you into a new life. What you meet on the way is part of the way.”

(John Tarrant, Sudden Awakening)

As philosopher Joseph Campbell once said, “Myths are public dreams and dreams are private myths,” and Moore’s Law is the myth that we chip makers and suppliers are publically living, hoping for EUVL as its enabler.  I and many others have dreamed that EUVL will happen and finally we are seeing the light (so to speak). Now we need to look at what worked and what did not, and why. What are the root causes of the problems we encountered, and how do we address them moving forward?

I have continued to promote EUVL as I have found this technology to be the right and elegant way to move forward. True solutions are often elegant and demonstrate “Satyam, Shivam, Sundaram,” a famous Sanskrit saying which can be translated in various ways but which more or less means that existence itself is enlightened and has been all along. These have been tough times and results are now speaking for themselves. I leave you with this quote from Mary Oliver:

Maybe the desire to make something beautiful

Is the piece of God that is inside each of us.


If being so beautiful isn’t enough, what

Could they (blue horses) possibly say?

(Mary Oliver, Franz Marc’s Blue Horses, Penguin Press)