Each year, Solid State Technology turns to industry leaders to hear viewpoints on the technological and economic outlook for the upcoming year. Read through these expert opinions on what to expect in 2018.
Enabling the AI Era with Materials Engineering
Prabu Raja, Senior Vice President, Semiconductor Products Group, Applied Materials
A broad set of emerging market trends such as IoT, Big Data, Industry 4.0, VR/AR/MR, and autonomous vehicles is accelerating the transformative era of Artificial Intelligence (AI). AI, when employed in the cloud and in the edge, will usher in the age of ‚ÄúSmart Everything‚ÄĚ from automobiles, to planes, factories, buildings, and our homes, bringing fundamental changes to the way we live
Semiconductors and semiconductor processing technol- ogies will play a key enabling role in the AI revolution. The increasing need for greater computing perfor- mance to handle Deep Learning/Machine Learning workloads requires new processor architectures beyond traditional CPUs, such as GPUs, FPGAs and TPUs, along with new packaging solutions that employ high-density DRAM for higher memory bandwidth and reduced latency. Edge AI computing will require processors that balance the performance and power equation given their dependency on battery life. The exploding demand for data storage is driving adoption of 3D NAND SSDs in cloud servers with the roadmap for continued storage density increase every year.
In 2018, we will see the volume ramp of 10nm/7nm devices in Logic/Foundry to address the higher performance needs. Interconnect and patterning areas present a myriad of challenges best addressed by new materials and materials engineering technologies. In Inter- connect, cobalt is being used as a copper replacement metal in the lower level wiring layers to address the ever growing resistance problem. The introduction of Cobalt constitutes the biggest material change in the back-end-of-line in the past 15 years. In addition to its role as the conductor metal, cobalt serves two other critical functions – as a metal capping film for electro- migration control and as a seed layer for enhancing gapfill inside the narrow vias and trenches.
In patterning, spacer-based double patterning and quad patterning approaches are enabling the continued shrink of device features. These schemes require advanced precision deposition and etch technologies for reduced variability and greater pattern fidelity. Besides conventional Etch, new selective materials removal technologies are being increasingly adopted for their unique capabilities to deliver damage- and residue-free extreme selective processing. New e-beam inspection and metrology capabilities are also needed to analyze the fine pitch patterned structures. Looking ahead to the 5nm and 3nm nodes, placement or layer-to-layer vertical alignment of features will become a major industry challenge that can be primarily solved through materials engineering and self-aligned structures. EUV lithography is on the horizon for industry adoption in 2019 and beyond, and we expect 20 percent of layers to make the migration to EUV while the remaining 80 percent will use spacer multi- patterning approaches. EUV patterning also requires new materials in hardmasks/underlayer films and new etch solutions for line-edge-roughness problems.
Packaging is a key enabler for AI performance and is poised for strong growth in the coming years. Stacking DRAM chips together in a 3D TSV scheme helps bring High Bandwidth Memory (HBM) to market; these chips are further packaged with the GPU in a 2.5D interposer design to bring compute and memory together for a big increase in performance.
In 2018, we expect DRAM chipmakers to continue their device scaling to the 1Xnm node for volume production. We also see adoption of higher perfor- mance logic technologies on the horizon for the periphery transistors to enable advanced perfor- mance at lower power.
3D NAND manufacturers continue to pursue multiple approaches for vertical scaling, including more pairs, multi-tiers or new schemes such as CMOS under array for increased storage density. The industry migration from 64 pairs to 96 pairs is expected in 2018. Etch (high aspect ratio), dielectric films (for gate stacks and hardmasks) along with integrated etch and CVD solutions (for high aspect ratio processing) will be critical enabling technologies.
In summary, we see incredible inflections in new processor architectures, next-generation devices, and packaging schemes to enable the AI era. New materials and materials engineering solutions are at the very heart of it and will play a critical role across all device segments.