2.5D announcements at the Global Interposer Tech conference

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December 6, 2011 - Practitioners, students and other interested parties assembled in Atlanta at the recent Global Interposer Technology workshop (GIT) on the Georgia Tech campus to discuss where the technology stands and where it is going.

Xilinx, the first to reach HVM with their Vitrex-7 2000T FPGA, detailed various aspects of their 2.5D interposer product. Suresh Ramalingam, senior director of advanced package design, announced that their Virtex product, which uses a 21mm × 26mm TSV interposer, has been sampled to customers since September and will be in full production in 2012. TSMC is fabricating the chip and the interposer, Amkor is bumping the chip and assembling the FPGA slices on the interposer, and Ibiden is fabricating the package substrate. Ramalingam emphasized that the interposer solution was necessary (vs. full 3D stacking) to insure proper thermal performance. Kumar Nagarajan of Xilinx called the use of the interposer the "low-risk, low-complexity approach." Both indicated that this 2.5D solution would be spreading to future Xilinx products.

Paul Franzon, professor of EE at NC State and long time 3D practitioner, compared the capabilities of SoC vs. 2.5D vs. 3D, agreeing that thermal performance was the outstanding feature of 2.5D. He also detailed the concept of "dark silicon" where most of the chip must be in "off mode" at any given time to meet predetermined power budgets. Low-power 2.5 and 3D solutions are expected to alleviate this situation.

Doug Yu, senior director of integrated interconnects and packaging at TSMC, had some significant comments on 2.5D interposer supply chain developments. While there have been many recent proposals for how module fabrication tasks would be divided between foundries, IDMs, OSATS, and possible 3rd party interposer suppliers, he proposed that for now the interposers should be built completely by one party, so that there is clear ownership and an efficient route to cost and yield improvements. Foundries which can leverage their Cu processing capability, offer no customer competition (vs. IDMs), and have the design support capabilities would be the natural source for interposers, he proposed -- and in fact that this is TSMC's plan. Rumors in the audience indicated that TSMC is currently only engaging selected 1st-tier customers with their interposer technology.

Byran Black, CTO of AMD, indicated that AMD is taking a "very broad view of TSV and stacking" and that the industry "will stagnate if we don't get 3D." He claimed that AMD has been involved in 3D for more than five years, but added that they are "intentionally not talking about what we're doing."

The audience certainly took notice when Black stated that AMD's "Southbridge" chip was probably the last that would be impacted by scaling. He envisions that in the future, chip companies will be focusing process node development on specific application functionalities -- this, he contends, will reduce mask layers and run time and increase yield while improving performance and reducing power requirements, area, and cost for each individual functionality. These separately fabricated functionalities would then be combined vertically and/or horizontally on an interposer to form the final circuit function.

Several GIT speakers touted the potential of glass as an interposer substrate material due to its perceived lower cost position, outstanding Rf performance, and its ability to be fabricated in large format. Glass producers in the audience such as Corning and Asahi indicated that they are actively pursuing glass interposer technology as part of the Georgia Tech consortium program. Henry Utsunomiya, president of Interconnect Technologies, further predicted that glass interposers would be used for FC-CPU and GPU starting in 2013. Christian Nopper, R&D director of ST Micro-Tours , indicated that glass substrates are already being used for their Rf IPADS technology (Integrated Passive and Active Devices).

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