December 29, 2011 - At the recent 7th annual RTI 3-D Architectures for Semiconductor Integration and Packaging (3D ASIP) Conference in Burlingame CA, the "buzz" centered around the presentation by TSMC's Doug Yu, senior director of integrated interconnect, who repeated the case he had made at the November Georgia Tech Interposer Conference [see "2.5D announcements at the Global Interposer Tech conference"] for the pure foundry model for 2.5 and 3DIC -- claiming that TSMC was readying to take on full beginning to end interposer manufacturing.
Yu told the audience of more than 200 that sharing the fabrication process with OSATs is not the preferred option for TSMC, because "the risk for the customer is too high [...] therefore we [TSMC] will take full responsibility and accept full risk." TSMC is proposing that such one stop shopping will be simpler, cheaper and more reliable than using multiple sources (i.e. foundries, assembly houses and potentially other partners). Yu remained steadfast in his assessment that the required investments and the technology needed to handle thinned wafers would require that the foundries take control of such processing: "This is a new ballgame; the old ways of doing business are out of date for this new technology." On rumors that TSMC is currently working with only a handful of 2.5D/3D customers (including Xilinx); he indicated that "new customers will have only the integrated solution proposal [...] some, but not all of them [customers] want us to work with other partners, but many like our new approach very much."
Certainly with customer Xilinx being first to enter the 2.5D market space, TSMC appears ahead of the rest of the foundries in this regard. Ivo Bolsens, VP and CTO of Xilinx detailed the company's Virtex 2000T FPGA product which he claims delivers 4× the compute performance of the current largest monolithic device [see "Xilinx, Elpida highlight SEMICON Taiwan's SiP Global Summit"].
Currently, TSMC is manufacturing the Xilinx chips and manufacturing and bumping the Xilinx interposer. Xilinx is using Amkor to assemble the FPGA chips on the interposer and the interposer into a BGA package. Since the interposers are using 65nm dual damascene processing for the multiple layers of RDL, in reality this is something that the assembly houses currently aren't equipped to handle.
When asked about the incorporation of other foundries chips onto the interposer or chip stack, Yu responded that there is no need to go to other foundries/IDMs except for memory, and that TSMC would partner with one or more memory suppliers to resolve that issue.
While all the OSATs have bumping and WLP processes capable of standard RDL fabrication, products have not yet been announced that would use such coarse dimensioned interposers (those with features over 5-10μm) -- and none of the OSATs have announced any intention to produce any interposers. "It is correct that we are not offering 'coarse' interposers, although we have capability to produce them," one OSAT requesting anonymity commented, "because we don't see ourselves competing in that space with foundries and don't think it will be a viable business worth chasing and investing capital and resources in." Eric Beyne, scientific director of advanced packaging at IMEC, during his presentation also questioned whether "coarse interposers" would provide enough value to be integrated into products.
Despite those comments, unsubstantiated rumors swirled at the conference that Siliconware (SPIL) had or was about to purchase a complete 2.5D/3D line from Applied Materials including dual damascene capability so they could enter into manufacturing of high-density interposers. Neither Applied nor Siliconware would confirm or deny the rumors -- but it was interesting that graphics chip maker Nvidia, an SPIL customer, also made a presentation and indicated that they needed 2.5D ASAP.
LeiLei Zhang of Nvidia, who declared "Scaling is ending. Let's get over it and move our resources elsewhere," indicated that Nvidia is likely to use a turnkey solution such as TSMC is offering with such 2.5D TSV solutions entering the Nvidia roadmap with their TESLA and CUDA high end networking GPU product lines.
While Altera's Bradley Howe, VP of engineering, predicted that "there are 8-10 years left to scaling, and then 3D will be the solution," he was quick to show 2.5D prototypes they are reading for the market, evidently a lot earlier than that. With archrival Xilinx already sampling the market with 2.5D products, that's probably a sound strategy.
Raj Pendse, VP and CMO at STATS ChipPAC, said the company is ready to handle mid-end through back-end interposer assembly processes and laid out the following roadmap for product introductions.