Interposer supply/ecosystem examined at IMAPS Device Packaging

March 12, 2012 -- At the recent IMAPS Device Packaging Conference in Ft McDowell, AZ, Solid State Technology's Insights from the Leading Edge (IFTLE) brought together a panel of manufacturers, users and market specialists to discuss the Evolving 2.5D / 3D Infrastructure.

Panel host and Solid State Technology contributing editor Phil Garrou was joined by Douglas Yu, Sr Director of front end and back end technology development for TSMC; Jonathon Greenwood, Director of Packaging R&D at GlobalFoundries; Remi Yu, Deputy Division Director of UMC; Nick Kim, VP of electronic packaging technologies at Hynix; Rich Rice, Sr VP of sales for ASE ; Ron Huemoeller, VP of Advanced 3D interconnect at Amkor; Matt Nowak, Sr Director of Engineering at Qualcomm and Jan Vardaman, President of TechSearch Inc.

Photo [l to r]: Yu (TSMC), Garrou (IFTLE), Huemoeller (Amkor), Vardaman (TechSearch), Greenwood (GlobalFoundries), Yu (UMC), Kim (Hynix), Nowak (Qualcomm), Rice (ASE).


While TSV technology appears to be stabilizing...

Panelists were unanimous in their descriptions of mainstream 3D packaging being represented by 5-8µm copper through silicon via (TSV) middle on 50µm-thick silicon from integrated design manufacturers (IDMs) or foundries and interposers as 10µm Cu TSV in 100µm-thick silicon. Vardaman from TechSearch points out that some larger TSV last from the backside are, of course, also being used in image sensors, and other TSV variations are being seen in micro electro mechanical system (MEMS) applications.


...the source of interposers has become much more obscure

When discussing interposer sourcing, Amkor’s Huemoeller indicated that only 3 players were close to being ready to deliver interposers of any kind: TSMC, UMC, and GlobalFoundries. While some in the audience were resolute in their conviction that only panel-size formats (i.e flat panel glass or laminates) could deliver the economics necessary to make 2.5/3D packaging mainstream, the assembled experts agreed that while glass panels and even possibly advanced laminates presented interesting possibilities for low-cost future products, they currently cannot meet requirements and are in the earliest stages of R&D.

If we assume interposers will be divided into the categories of "coarse" and "fine," the infrastructure question becomes "Where will these interposers be coming from?" Fine interposers by definition (1µm l/s) will require front-end semiconductor manufacturing tools and thus will be restricted to today’s IDM and foundries that have such capability in place.

Table. Overview of 2.5D/3D packaging interposer technologies.
Interposer features Coarse Fine
Metal l/s (um) >5/5 <1/1
??? foundries
RDL metal Cu Al, Cu
RDL thickness (um) 3-5 <1
Passive devices yes yes
Cost lower higher
Application low I/O high I/O

While all the outsourced semiconductor assembly and test (OSAT) providers have redistribution layer (RDL) technology capable of fabricating “coarse” interposers, so far none of the major players -- ASE, Amkor, SCP, SPIL -- have announced that they are entering the interposer business. Insights from the Leading Edge directly contacted each OSAT recently, and all four confirmed that position.

TSMC, UMC, and GlobalFoundries all indicated that they will be commercializing fine-featured interposers, although, as of yet, only TSMC and IBM have initiated small-volume product production.

When asked about rumors circulating that OSATS are looking to put front-end equipment in place to manufacture fine-pitch interposers, both Amkor and ASE indicated that they had no plans to do so. Amkor’s Huemoeller responded that foundries would be supplying interposers and they [Amkor] would be assembling them. ASE’s Rice agreed short term, but indicated that longer term they envisioned future applications where coarse interposers would find their niche and be an important part of the technology base.


2.5D economics and mobile product requirements

Qualcomm’s Nowak indicated that interposers would add substantial cost and as such probably would not be a broadly accepted solution for low cost mobile products which would prefer straight 3D stacking. In response to the Qualcomm statement, TSMC’s Yu responded that indeed the addition of an interposer added cost to the overall component, but that “...this [2.5D] solution also offers cost savings by reuse of IP and separating digital and analog circuitry and allowing partitioning of costly SoC” and that this could make it the lowest-cost solution.

Based on the positions of these experts, one can conclude that initial interposer supply will be so-called “fine featured” high-end product, which will be provided today by foundries/3D-active IDMs. While we can anticipate that there will be products in the future that can be designed to take advantage of “coarse” interposers, and some of the initial fine interposer activities such as graphics applications might be able to migrate to such “coarse” interposers as they become available, we will, initially at least, be limited by the availability and cost of foundry-supplied interposers.


Options for the evolving infrastructure

Due to numerous technical challenges that make the conventional collaboration infrastructure more difficult for 2.5/3D, Yu indicated that TSMC takes the position of strongly favoring controlling and being responsible for the full process. Yu indicated that they would have partnerships in place to supply the required memory, although these partners were not identified.

In contrast, UMC and GlobalFoundries indicated a preference to work under the open ecosystem model, where chips from various vendors could be stacked and assembled by OSAT partners.  Both of the OSATs, as would be expected, favored the open ecosystem model where chips from various suppliers would be assembled at the OSATS.

When asked how the current economic issues surrounding Elpida were affecting the UMC/Elpida/PTI partnership, UMC’s Remi Yu responded that this was only one 2.5/3D engagement and that they were moving forward with others.


Memory stacks coming from Hynix

When Hynix was asked whether they would be offering memory stacks containing TSV, as have been already announced by Samsung, Micron, and Elpida, Hynix’s Kim responded that he expects Hynix “2 and 4 chip memory stacks with TSV to be in mass production in 2013 and graphics solutions on interposers in 2014.”


Direct copper interconnect still a ways off

When asked what was limiting direct copper/copper (Cu-Cu) bonding of the stacks, the panelists all agreed that copper bonding was not ready for prime time just yet. Yu, a strong proponent of copper interconnect, noted that current copper bonding options have yield issues that have not yet been overcome. “Current requirements for pads are too large and the required CMP of the interfaces is causing dishing that must be handled...HVM [high-volume manufacturing] of copper-copper bonding options is tougher than showing research samples.”


Addressing 2.5/3D product rumors

Rumors abound that TSMC is designing the Apple A6 processor for iPads and iPhones with 3D TSV. When asked to comment on this, or whether Samsung was also offering TSV in their design of the A6, TSMC’s Yu offered the expected “no comment,” and silence came from the rest of the panel. Similarly, no one would offer up comment about who would be supplying Sony, who announced that they would require TSV interposers for their next Playstation upgrade.

When asked about timing for the expected HVM of wide IO memory stacks for tablets, Qualcomm responded probably 2013 and Hynix responded maybe 2015.

Dr. Phil Garrou is a contributing editor to Solid State Technology and regular blogger, filling Insights from the Leading Edge with conference highlights and news analysis for the advanced semiconductor packaging sector.


Volume 55, Issue 4

Article Archive for Advanced Packaging.


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