STATS ChipPAC expands TSV work into mid-end-of-line


August 29, 2012 - STATS ChipPAC, Fremont, CA, says it has expanded its through-silicon via (TSV) capabilities by qualifying a 300mm mid-end manufacturing operation and transition to low-volume manufacturing.

STATS ChipPAC was one of the first outsourced semiconductor assembly and test (OSAT) providers to invest in through-silicon via (TSV) technology for back-end-of-line (BEOL) semiconductor manufacturing, specifically 2.5D (silicon interposers) and 3D TSV on 200mm wafers, with chip/chip and chip/wafer assembly using stealth dicing and fine-pitch microbump bonding down to 40μm. A year ago the company began expanding into TSVs for 300mm mid-end-of-line (MEOL) processing capabilities, steps that occur between wafer fabrication and back-end assembly. These include microbump technology down to 40μm, temporary bond/de-bonding, backside via reveal, isolation, and metallization.

"During the implementation phase of our mid-end TSV operation, we investigated multiple process options and identified key cost variables that would affect the commercialization of this technology," said Dr. Han Byung Joon, STATS ChipPAC's EVP and CTO. "We now have mid-end manufacturing capacity in place in Singapore and are actively engaged with multiple strategic customers on the production qualification of 2.5D and 3D packaging designs."

The company says it is "firmly engaged with multiple strategic customers" in TSV development programs. Current 3D TSV development and customer qualification activities include devices at the 28nm silicon node, application processors and graphic processors utilizing TSV to match the needs of higher-bandwidth applications for the mobile market.

(Image via Stats ChipPAC)

Font Sizes:


Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. 


Electroiq 2 EIQ2


Automated Test Creation for Mixed Signal IP using IJTAG

The creation of test patterns for mixed signal IP has been, to a large extent, a manual effort. To improve the process used to test, access, and control embe...

Faster Time to Root Cause with Diagnosis-Driven Yield Analysis

This whitepaper describes the benefits of implementing a diagnosis-driven yield analysis flow using the Tessent® Diagnosis and Tessent YieldInsight® software...


Innovation in Semiconductor Manufacturing Instrumentation

As the industry is incorporating more MEMS devices with integrated magnetic sensors, they are encountering challenges that cannot be overcome with ...

3D and 2.5D Integration: A Status Report Live Event

This webcast will explore the present status of 2.5 and 3D integration, including TSV formation.

Questions and answers on FD-SOI

Fri Jan 04 14:56:00 CST 2013

Present your ideas at The ConFab in 2013

Mon Nov 26 09:04:00 CST 2012

The ConFab 2013 countdown begins

Thu Aug 09 16:18:00 CDT 2012

The ConFab: Big data is here

Sun Jun 03 19:19:00 CDT 2012

Oh, snap!: Pics from The ConFab

Sun Jun 03 19:09:00 CDT 2012



Volume 56, Issue 1

Article Archive for Solid State Technology.

© 2013. PennWell Corporation. All Rights Reserved. PRIVACY POLICY | TERMS AND CONDITIONS