Monolithic 3D is now on the roadmap for 2019

Zvi Or-Bach, President & CEO of MonolithIC 3D Inc. blogs about the appearance of 3D integration on several roadmaps.

At the recent CEA Leti day, that took place as part of Semicon West2013, Laurent Malier, Leti CEO, presented his “A look at the coming Decade.” Slide 15 of the presentation provides Leti’s vision for CMOS roadmap:

Monolithic 3D is presented on Leti’s roadmap as the technology to follow the 7nm process node.

Early this year we blogged IEDM 2012: The pivotal point for monolithic 3D ICs. It is now quite reassuring to see monolithic 3D now as part of the industry roadmap. We discussed then that memory vendors are already gearing up for volume production of the 3D NAND. And, indeed, just this summer, Toshiba has been reported to leverage the monolithic 3D cost reduction advantage (Toshiba to Build Fab for 3D NAND Flash). It only makes senses for the CMOS market to follow.

Doubters would ask why the industry would introduce a new dimension to the roadmap that has been extremely successful for over 40 years. The answer is very simple – because it is not so successful anymore. We are all aware that the escalating costs of lithography had diminished transistors cost reduction, as is illustrated in the following ASML chart:

Even if we ignore the cost issues we should remember IBM’s Bernie Meyerson caution that “atoms don’t scale.” We are quickly approaching these limit as is visible on the following Intel chart:

Accordingly, Mike Mayberry, director of component research at Intel, said at the recent IMEC Technology Forum that he“has looked down the highway of conventional silicon development and reckons things become foggy beyond about the 7-nm node.” In fact, in his March 2013 presentation “Pushing Past the frontiers of Technology” Mike Mayberry also presents monolithic 3D on his road map:

This transition was well captured in the title of 2011 IEDM keynote address by Mark Bohr, the Senior Fellow of Technology and Manufacturing Group and a Director of Process Architecture and Integration of Intel, “The Evolution of Scaling from the Homogenous Era to the Heterogeneous Era.”


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