Planar fully depleted silicon-on-insulator (FDSOI) technology represents an important device architecture for continued CMOS scaling. Its advantages include excellent short-channel electrostatics, un-doped channels and effective back bias for performance boost and leakage lowering. Moreover, FDSOI is fabricated using a more conventional, lower-cost process than more complex FinFET architectures. Researchers from STMicroelectronics and the IBM Technology Development Alliance will discuss the successful implementation of strained FDSOI devices with gate lengths, spacers & buried oxide (BOX) dimensions compatible with design rules of the 10nm technology node.
Two additional enabling elements for scaling FDSOI devices to the 10nm node will be reported: advanced strain techniques for performance improvement, and reduced BOX thickness for better SCE & higher body factor. The researchers also will report the first demonstration of strain reversal in strained SOI by the incorporation of SiGe in a short-channel PFET device. With regard to performance, at 0.75V the devices achieved a competitive effective drive current of 340 μA/μm for NFET at Ioff=1 nA/um, and with a fully compressively strained 30% SiGe-on-insulator (SGOI) channel on a thin (20nm) BOX substrate, PFET effective drive current was 260 μA/μm at Ioff=1 nA/um. Competitive sub-threshold slope and DIBL also will be reported.
Condensation temperature was determined to strongly influence channel quality. A low-temperature process was developed to form a defect-free SiGe channel from the strained SOI starting substrate. The two images are top-down scanning electron microscope views showing the results of a high-temperature process (left) and the low-temperature process (right).
(Paper #9.1, “FDSOI CMOS Devices Featuring Dual Strained Channel and Thin BOX Extendable to the 10nm Node,” Q. Liu et al, ST Microelectronics/IBM Technology Development Alliance)