SRC and MIT extend high resolution lithography capabilities

MIT researchers sponsored by Semiconductor Research Corporation have introduced new directed self-assembly (DSA) techniques that promise to help semiconductor manufacturers develop more advanced and less expensive components.

The MIT study demonstrates that complex patterns of lines, bends and junctions with feature sizes below 20nm can be made by block copolymer self-assembly guided by a greatly simplified template. This study explained how to design the template to achieve a desired pattern. Electron-beam lithography was used to produce the template serially, while the block copolymer filled in the rest of the pattern in a parallel process. This hybrid process can be five or more times faster than writing the entire pattern by electron beam lithography.

Related new: EUV is late but on the way for 10nm; DSA is promising

“We believe our research will help Moore’s Law to be continued,” said Caroline Ross, MIT professor of Materials Science and Engineering. “To increase the density of transistors in a given area, the pitch of the features in a transistor should be scaled down, but the increasing time and cost of manufacturing such fine and dense features becomes more problematic. Our research suggests a solution to this problem.”

Leveraging block copolymer self-assembly to produce dense, high resolution patterns was proposed and demonstrated several years ago, but there was no systematic way to design templates to achieve a complex block copolymer pattern. The MIT study developed a simple way to design a template to achieve a specific block copolymer pattern over a large area. Although the work used electron-beam lithography to define the template, other methods such as photolithography with trimming could be used to produce the templates.

Block copolymer lithography is already on the semiconductor industry roadmap as directed self-assembly, but the process is still in its infancy. Although DSA patterning has been demonstrated on 300 millimeter wafers, these early trials used templates fabricated by photolithography with limited resolution and limited control of the feature geometry. The MIT process offers a path to far more complicated geometries using relatively simple templates. Next steps involve the research being shared with semiconductor companies for further studies.

“The demand for computing processors with higher bandwidth and memories of larger capacity continues to grow, but the manufacturing cost of these devices is also increasing as the transistor and associated interconnect dimensions shrink,” said Bob Havemann, Director of Nanomanufacturing Sciences at SRC. “Lithography research such as the work completed by the MIT team is critically important as the required feature sizes in semiconductor manufacturing scale below what is achievable with conventional lithography techniques.”

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  1. Pingback: The Week In Review: February 28, 2014 | Semiconductor Manufacturing & Design Community

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