Will interconnect manufacturing requirements cramp Moore’s Law’s style?

By Vidhya Ramachandran

The recent years have seen considerable contention in the semiconductor industry on whether Moore’s Law is alive and well [1], [2], [3]. The impact of on-chip interconnect cost on advanced node technology products, in particular, has generated much discussion [4] and, some would say, discontent [5]. Beyond 28nm, BEoL cost and complexity projections (Figure 1) show an explosion and at the upcoming 10nm node, on-chip interconnect costs are projected to exceed 50 percent of the SoC cost [4]. Technologists from multiple functions in the semiconductor industry have to come together to address this issue, as will be evident at the Workshop “Manufacturing of Interconnect Technologies: Where Are We Now And Where Do We Go From Here?” to be held prior to the International Interconnect Technology and Advanced Metallization Conference (IITC/AMC) on May 20 in San Jose.

Figure 1. From [4], BEOL cost and mask count estimates for advanced nodes. Note the sharp rise beyond 28nm, driven by multiple patterning.

Figure 1. From [4], BEOL cost and mask count estimates for advanced nodes. Note the sharp rise beyond 28nm, driven by multiple patterning.

Particularly challenging at the 10nm and 7nm nodes is lithography. The incumbent is 193i technology, which is now being used to print significantly sub-wavelength features [1]. At the 20nm node this has been accomplished by double patterning, but approaching 7nm this will require triple patterning, a new wavelength (e.g. EUV), or some other disruptive technology. This, in addition to a steep rise in the number of metal layers in order to route a higher density of transistors and more complex circuitry, influence mask count, process complexity and cycle-time, directly hitting at the heart of cost and yield. Photolithography researchers from GLOBALFOUNDRIES will review advancements in lithography that enable solutions for these issues at the IITC/AMC Workshop.

Many new materials are being introduced to meet RC requirements, such as lower K insulators and thinner and self-formed metal barrier layers [7]. These implementations are not stand-alone changes, but come hand-in-hand with their respective versions of etch, CMP, cleans and so on, moving into new process condition regimes [8], [9]. While these modules pose challenges in development, in manufacturing, where thousands of wafers could be at risk from a single process going out of control, new materials can be particularly problematic. These challenges are driving development of innovations in the methodology for introduction of new materials and processes, process control and yield management for advanced technologies at several industry leaders. New defects and failure mechanisms are being discovered and solved; new metrology methods are enabling more robust process control; and pervasive implementation of automated process control (APC) prevents process excursions.

As we are well-aware, aspects of semiconductor manufacturing that could act independently in the past such as design and process now have to work closer together throughout the entire life-cycle of a product, from conception to manufacturing ramp [11]. We increasingly find that successful manufacturing is driven by “yield-aware” design, with robust follow-up between designers and manufacturers during the fabrication phase [12]. Designers from ARM highlight the interconnect-related challenges of implementing their high performance cores in SoCs at 16 nm and beyond.

The transition to 450mm wafers is often touted as a significant cost breakthrough; however any significant cost savings from the transition to 450mm wafers will be strongly dependent on manufacturability readiness [13]. Reports from researchers at the Global 450mm Consortium (G450C) on the status of this readiness underscore joint industry initiatives, standards and equipment supplier engagement.

With the acute focus on challenges in interconnect manufacturing with meeting Moore’s Law projections, interconnect technologists have their work cut out for them. However, the upside is that there is plenty of opportunity for innovation across the board. Some of this will be in evidence at the Panel Discussion to follow the IITC/AMC Workshop, where industry leaders will share their perspectives on how the industry will meet these challenges while remaining cost competitive. As we know, semiconductor engineers are a resourceful lot, and we look forward to all the exciting developments in store for us!

Vidhya Ramachandran is an Advanced Interconnect Technology Engineer at Qualcomm Technologies, Inc. and a co-organizer of the IITC/AMC 2014 Workshop titled ““Manufacturing of Interconnect Technologies: Where Are We Now And Where Do We Go From Here?”. Deepak Sekar, a Director at Rambus Labs, and General Co-Chair of IITC/AMC 2014 also contributed to the article.


[1]    http://www.eetimes.com/author.asp?doc_id=1321536

[2]    http://www.eetimes.com/document.asp?doc_id=1263256

[3]    http://www.eetimes.com/author.asp?section_id=36&doc_id=1321784&page_number=1

[4]    “Smart Mobile SoCs Driving the Semiconductor Industry: Technology Trend, Challenges and Opportunities”, Geoffrey Yeap, IEDM 2013.

[5]    http://semiengineering.com/executive-viewpoint-qualcomm-on-process-technology/

[6]    “Scope and Limit of Lithography to the End of Moore’s Law”, Burn Lin, ISPD 2012.

[7]    ITRS Interconnect Workgroup 2012 Winter Update

[8]    http://www.evaluationengineering.com/news/imec-addresses-3-d-ics-interconnects-cryogenic-etching-and-solar-cells.php

[9]    “Materials Challenges in Planarization and Interconnect Technologies”, Mansour Moinpur, International Conference on Planarization/CMP Technology 2007

[10] http://www.techdesignforums.com/practice/technique/euv-options-sub-20nm/

[11] http://edn.com/design/integrated-circuit-design/4412868/Design-for-manufacturing-and-yield

[12] http://www.semiwiki.com/forum/content/1054-tsmc-28nm-yield.html

[13] http://electroiq.com/blog/2013/06/450mm-_-it_s-bigger-than-you-think/


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