Down to 5nm: Scaling with the usual suspects - performance, cost

By Debra Vogler, SEMI

The semiconductor industry never lacks for challenges and/or controversy as it forges ahead from one technology node to the next. “Lithography is always a challenge,” observes Dick James, senior technology analyst at Chipworks. While there may be a non-EUV roadmap to 7nm, what will happen by 5nm is not so clear, except “by the time the industry gets to 5nm, silicon will have run out of steam,” said James. His recitation of the coming mountains to climb is extensive: integration of new materials, contact resistance of ever-smaller contacts, pitch quartering, contact etch and self-aligned vias, shrinking the gate stack, and modifying work function materials. And that’s just the front-end!

“The big divide at the moment is FDSOI vs FinFET,” James told SEMI. “If IBM survives, I could see them following the FDSOI route, but the rest of the industry seems to be going FinFET. By the time we get to 7nm and 5nm it will likely be moot, we’ll have to do something else such as nanowires…in the end, it all boils down to performance vs. cost.”

With respect to performance and scaling, Soitec’s SVP of Digital Electronics Division and FDSOI guru Christophe Maleville, a clear proponent of SOI-based technology, told SEMI that a key challenge is delivering a worthwhile performance increase while allowing very low energy consumption. “In the PC era, performance was king,” observed Maleville, who will speak at SEMICON West 2014. “Although power consumption was obviously a concern, it was okay to trade GHz for high leakage current. With the advent of the mobile, always-on device era, the weights of priorities have shifted.” With mobile applications driving the industry, performance must also take into account low heat dissipation and battery life. “Delivering high drive current is one thing – and FinFET appears to be pretty good at that – but this has to be weighed against the other parameters that affect the actual in-application performance of the chip.”

Medium-term, i.e., down to the 10nm node, Maleville said that while there is a choice in transistor technology between FDSOI and FinFET, the latter has its challenges (Figure 1). At 14nm and below, particularly for bulk silicon, Maleville cites issues such as controlling substrate leakage and maintaining good variability. “In addition, because of its 3D architecture, parasitic capacitance of the FinFET device is relatively high and scaling means reducing the pitch into which FinFET transistors need to fit, which does not go in the direction of limiting (fringe) parasitic capacitance” said Maleville. “Beyond 14nm, these challenges will become even more pressing.” Doing FinFET on SOI can help alleviate some of these challenges because it offers intrinsic isolation under the fin, thereby removing the need for a complex-to-optimize punch-through stopper junction. “It also eliminates some variability associated with the doping this junction requires.” FinFET on SOI also aids in the manufacture of fins with well-defined height, “therefore, ensuring no excessive variability from fin geometry fluctuations.”

Fig. 1

Fig. 1

FDSOI technology is not without its own set of challenges. “The electrostatic control of an FDSOI transistor is, in principle, not as good as that of a multi-gate device,” Maleville explained. “On the other hand, FDSOI is less subject to some of the pains associated with scaling FinFETs, such as keeping parasitic capacitance low enough, or keeping variability (including that originating from transistor geometry variations) under control.” Figure 2 illustrates the value that using SOI brings (for FD-2D technology) in terms of silicon geometry control and uniformity.

Fig. 2

Fig. 2

With respect to scaling FDSOI technology to 14nm, Maleville noted that excellent results were reported at IEDM 2013 and that both Leti and STMicroelectronics are showing roadmaps to scale FDSOI down to 10nm, with introduction of Ge in the channel, along with further source/drain optimization and the option to use strained SOI. With respect to starting SOI wafers, the key areas of work already underway according to Maleville are: 1) ensuring excellent thickness uniformity of the thin silicon layer, which needs to be improved from one node to the next; 2) reducing the thickness of the buried oxide from one node to the next, and 3) continuing to provide ultra-thin layers of top silicon with state-of-the-art defectivity required at each node.

Industry experts interviewed on the topic of scaling are in agreement about new device architectures (e.g., gate-all-around, nanowires, tunnel FET, etc.) along with new materials (e.g., Ge and III-V compound semiconductors). Regarding the introduction of new materials, Maleville notes that the following will have to be considered: 1) demonstrating at the device level that there is a CMOS solution based on the new materials that deliver better results than silicon in the power supply and geometrical dimension ranges envisaged for the 7nm-5nm nodes, and 2) finding a way to implement Ge or a III-V material of suitable quality for good transistor behavior. “The Smart Cut layer transfer technology employed to fabricate SOI wafers has a role to play here,” said Maleville. “In particular, transferring germanium or III-V materials onto an oxidized silicon base (i.e., doing GeOI or III-V.OI) can be an interesting alternative to epitaxial growth of these materials on a bulk substrate.”

Because of lattice mismatch, Maleville further explained that epitaxial growth of Ge or III-V on silicon is challenging and achieving decent material quality is difficult. Though the alternative approach of Smart Cut-based layer transfer comes with its own set of challenges (defectivity, etc.), “it has the advantage of allowing the slice of a high-quality layer from a donor that can have defects outside the transferred layer, and the ability for this donor to be recycled multiple times.”

Enter CNTs

While the industry winds its way through the myriad choices of lithography technologies, transistor architectures, and materials choices, experts note that once the industry gets to 5nm, something new will have to happen. One technology getting close scrutiny is carbon nanotube (CNT) logic transistors. H.S. Philip Wong, the Willard R. and Inez Kerr Bell Professor in the School of Engineering and Professor of Electrical Engineering at Stanford University, told SEMI that transistors made with carbon nanotubes as the channel material hold special promise. The promise is due to the ultra-thin body of the carbon nanotube being only about one nanometer, while at the same time retaining excellent carrier transport properties. “No other bulk semiconductor has this unique advantage that allows the carbon nanotube transistor to scale to the shortest possible gate length,” said Wong (Figure 3).

Fig. 3

Fig. 3

The key issues in bringing CNT logic transistors to the forefront, noted Wong, include: 1) contact resistance (reducing the transfer length of the contact); 2) maintaining good carrier transport while meeting electrostatic requirements; 3) having a coordinated effort in industry (as exemplified by how the semiconductor industry solved the high-k/metal gate problem); and 4) taking a practical approach and recognizing that exotic, non-FET-based devices will not meet the time line of the industry for the 5nm node.

Recent developments of CNT transistor technology for digital logic include the synthesis of fully aligned carbon nanotubes on a wafer scale, device fabrication of high-performance carbon nanotube transistors, 3D integrated carbon nanotube circuits, low voltage (0.2 V) operation of carbon nanotube transistors, and compact models for circuit simulation. Performance benchmarking of carbon nanotube transistors with conventional CMOS at the device and the full-chip processor level have also been accomplished, along with the demonstration of circuits and complete systems.

Interested in learning more about the industry getting down to the 5nm node? Come hear from Soitec, imec, Intermolecular, GLOBALFOUNDRIES, SEMATECH, Stanford University, and G450C at the SEMICON West 2014 Semiconductor Technology Symposium (STS)  session titled “Getting to 5nm Devices: Evolutionary Scaling to Disruptive Scaling and Beyond.”  For information about this program, the agenda or pricing, please visit SEMICON West 2014 will be held July 8-10 at the Moscone Center in San Francisco.


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2 thoughts on “Down to 5nm: Scaling with the usual suspects - performance, cost

  1. Anil Kumar

    I feel to create a channel length of 5nm or less, a reliable lithography technique/tool need to be developed. A quite challenging but achievable task.
    Anil Kumar

  2. Martini Tech

    I do not think radical innovations, at least from the lithography point of view, are needed to reach the 7nm-5nm node.
    At Intel research and development for the 10nm node is already finished and 7nm is already well under way.

    Immersion lithography and multiple patterning are already may already bring us to 5nm without any need of EUV or fancy exotic technology, the only big issue being the raising costs of lithography.

    The new challenge will likely be to reduce the cost of lithography with new techniques (nanoimprint and DSA being the most likely candidates) rather than pushing the patterning to its limits.


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