Superfast stress inspection for overlay control

Tighter overlay requirements are motivating device manufacturers to explore new ways to characterize and manage overlay to improve yield. 


Control of overlay in multi-layer devices structures has always been important in semiconductor fabrication. The understanding and control of stresses accumulated during device fabrication has becoming more critical at advanced technology nodes. Within-wafer stress variations cause local wafer distortions which in turn present challenges for managing overlay and depth of focus during lithography. As devices shrink, the overlay require- ments become more and more stringent (FIGURE 1). The tighter overlay requirements are motivating device manufacturers to explore new ways to characterize and manage overlay to improve yield. The overlay budget includes contributions from the lithographic scanner, the reticle and the wafer. The wafer represents the largest source of overlay variability during high-volume manufacturing. Therefore, the development of an inspection strategy to control within-wafer and wafer-to-wafer variability may provide the key to meeting the challenges associated with future generations of devices.

Traditional wafer warpage or distortion measurements have typically used point-by-point measurements to generate low-density maps of the wafer geometry with a few hundred data points across the wafer. Depending on the specific technique, a higher density map may be possible at the expense of throughput or limiting the measurement to a small portion of the wafer. The trade-off of point density and throughput has meant that the use of wafer distortion characterization for overlay control has been limited to off-line process development and not to improve yields.

FIGURE 1. As devices shrink, the overlay requirements become more and more stringent.

The Superfast system based on the Coherent Gradient Sensing (CGS) interferometer uniquely provides high-density front-side pattern wafer maps (>3,000,000 data points) with fast data acquisition (seconds per wafer). The high throughput along with small foot print leads to a low cost of ownership relative to competing technologies.

This article discusses using deformation data from the front-side of a patterned wafer on the Superfast, we are able to understand the relationships between surface displacements, stress and overlay. It also reviews a case study evaluating the role of millisecond annealing parameters on overlay and stress.

Superfast (CGS) technology description

The CGS interferometer is a type of lateral shearing interferometer. The interference is generated in a self-referencing manner using two parallel diffraction gratings. This self-referencing approach eliminates the need for an independent reference beam from, for example, a flat mirror and ensures excellent fringe contrast regardless of the reflectivity of the surface under investigation. This is a key differentiator to accurately measure patterned wafers.

The interferometer essentially compares the relative heights of two points on the surface that are separated by a fixed distance, called the shearing distance. Physically, the change in height over a fixed distance provides slope or tilt information and the fringes in a CGS interference pattern are contours of constant slope. The slope data derived from the interference patterns is integrated numerically to generate the surface shape or topography.

Application to thin film stress measurement

The Superfast inspection system is designed for semiconductor manufacturing based on the CGS interferometer. The Superfast tool features a collimated probe beam of >300mm in diameter that is expanded from a relatively low power HeNe laser. The probe beam illuminates the entire wafer at once and the wafer is supported on three lift pins, which are then subtracted from the final analysis. The beam that reflects off of the wafer surface is distorted in accordance with the local height variations of the wafer. The distorted beam is steered through the two parallel diffraction gratings to generate an interference pattern that is imaged on to a CCD array. As a result, the wafer surface is mapped with high resolution (>3,000,000 data points) with measurement times of seconds.

FIGURE 2. Typical results from the Superfast inspection system, designed for semiconductor manufacturing based on the CGS interferometer.

Data integrity on patterned wafers is further enhanced through the implementation of phase shifting. Phase shifting is achieved by moving the gratings in the direction parallel to the shearing direction. Phase shifting provides several advantages and for the measurement of patterned wafers. The most notable being that fringe contrast in the interference fringes, that modulate with phase shifting can effectively be separated from pattern contrast, which is static with phase shifting. Phase shifting along with the inherent self-referencing nature of the CGS technique results in relatively high measurement integrity on patterned wafers without the need for dedicated or distinct targets, pads or other specialized features in the layout. Typical results are shown in FIGURE 2.

Compared to other techniques, Superfast has several distinct advantages.

  • Front Side Pattern Wafer Measurement: Core CGS 3G technology has been used to measure front-side of pattern wafers for over a decade.
  • High Data Density: Superfast generates high density maps of surface displacements that feature more than 3,000,000 points of data. In this manner, detailed within-die, die-to- die and wafer-to-wafer process variations that lead to overlay errors can be characterized.
  • High Throughput/Low Cost: The Superfast data set consists of interferometric images of the full wafer. These images can be captured rapidly using CCD camera, providing system throughputs of 100-150 wafers per hour.
  • Flexible Implementation: Superfast is capable of evaluating overlay at any step in the process flow and does not rely on dedicated overlay targets. In this manner, Superfast provides the ability to catch potential overlay problems due to process excursions upstream of lithography, thereby reducing material- at-risk and the need for subsequent scrap or rework. 
FIGURE 3. Displacement vector maps of the displacement residuals computed using a linear inter-field and intra-field correction.

FIGURE 3. Displacement vector maps of the displacement residuals computed using a linear inter-field and intra-field correction.

Case study: millisecond anneal characterization

This section describes a case study to illustrate the application of Superfast technology to characterize a millisecond anneal process. Four wafers of a full-flow 65nm device were annealed using Laser Spike Annealing (LSA). The device contained silicon germanium with 20% Ge. The four wafers were processed at peak annealing temperatures of 1235 or 1270oC and annealing times of 200 or 400 microseconds. Process-induced deformation information was collected by measure pre-anneal and post-anneal wafer topography using the Superfast system. After millisecond annealing, the wafers were processed through to contact patterning. Overlay data was collected post-lithography for all four wafers. The overlay was measured at 9 sites per shot for 28 shots. Surface displacement data was extracted at the same nominal locations on the wafer and displacement residuals were computed using linear inter-field and intra-field correction.

The displacement vector maps of the displacement residuals computed using a linear inter-field and intra-field correction are shown in FIGURE 3. Inspection of Fig. 3 reveals that the vector maps for the 1235oC temperature conditions (Figs. 3a & 3b) as well as the 1270oC / 200μs condition (Fig. 3c) all exhibit similar features such that the displacement vectors are generally in the same direction at a particular location in those three vector maps with the same relative vector magnitudes within-wafer. On the other hand, the vector map for the 1270oC / 400μs anneal (Fig. 3d) shows a fundamentally different distortion characteristic, indicating perhaps a change in deformation mechanism associated with the higher thermal budgets. This data suggests that wafer distortion measurements may provide a relatively efficient way to study transitions in mechanisms that occur under different processing conditions.

The correlation between the surface displacement residuals and the overlay residuals is shown in FIGURE 4. The data in Fig. 4 is based on the |mean|+3 sigma values of both quantities as evaluated at the locations shown in the vector maps of Fig. 3. There are several features of the plot in Fig. 4 that are notable. First, the corre- lation between overlay residuals and displacement residuals is excellent with a correlation coeffi- cient, r=0.985. Second, the extrapolation of the best-fit straight line to a displacement value of zero indicates a corresponding finite and positive overlay value of ~0.2. This result is not unexpected, since it is anticipated that other factors such as pattern placement error, lens errors and wafer distortion from other processes will contribute to the total overlay error. As such the overlay axis intercept provides an estimate of those other factors. Third, the slope of overlay versus displacement line is <1. A slope of less than 1 is consistent with the concept discussed in section 3, that the non-uniform stress component of the displacement field is related to the force acting along the interface or potential for mis-alignment. In this respect, it represents perhaps the maximum expected mis-alignment and the resulting overlay error will be some fraction of the ‘potential’ (i.e. slope <1). In addition, the slope value indicates that surface displacement is a more sensitive metric than overlay in that for the same process variability, surface displacement will change more rapidly than overlay.

FIGURE 4. The correlation between the surface displacement residuals and the overlay residuals is shown.

FIGURE 4. The correlation between the surface displacement residuals and the overlay residuals is shown.

Summary and conclusions

The tightening of overlay budgets at advanced technology nodes has led to a greater importance in understanding and when possible controlling wafer distortion. This paper has provided a description of a novel measurement and analysis approach to quickly and efficiently evaluate the effect of process-induced deformation on surface displacement and its relation to overlay errors. The millisecond annealing case study showed excellent correlation between the displacement residuals and overlay residuals with the correlation coefficient of 0.985. Utilizing the fundamental advantages of the CGS technology, the superfast is well suited for front- side patterned wafer topography measurement. The system allows for rapid measurement of wafer distortion and surface displacement with very high system throughputs. Data maps consisting of >3,000,000 data points can be acquired in seconds on patterned wafers without the need for special targets or dedicated structures.


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