Global shutter image sensors

Different GS pixel architectures and technologies are presented and performances compared. 


CMOS image sensors are in widespread use today in many consumer and professional applications. The typical shutter type for most CMOS image sensors is a so-called Rolling Shutter (RS). This is an inherent property of the 4T active pixel and its derived architectures with shared amplifier readout. The main drawback of a RS CMOS imager is that the start and the stop of the exposure is slightly shifted from pixel line to pixel line resulting in object deformation of fast moving objects (FIGURE 1) or the so-called “jello” effect when the camera is vibrating. To avoid this, either a mechanical shutter or a flash is required. Neither of these is accepted in many applications.

FIGURE 1. Rolling shutter image artifacts in the spokes of the turning wheel

FIGURE 1. Rolling shutter image artifacts in the spokes of the turning wheel

The alternative is using a so-called Global Shutter (GS) pixel based image sensor, whereby every pixel of the entire pixel array acquires the image during the same time period. This requires an in-pixel memory element that stores the signal after capture by the photodiode. Interline transfer (IT) CCDs were for many years the technology of choice for GS imagers, due to the combi- nation of global shutter with low read noise through a correlated double sampling (CDS) output stage. However, compared to CMOS image sensors, CCDs are limited to moderate readout speeds, consume more power, and lack on-chip integration of timing and AD conversion circuitry.

The first generation of GS CMOS imagers suffered from high read noise due to the lack of CDS on the charge sense node, and from poor shutter efficiency. Today, several techniques have been proposed to combine CDS with GS functionality. Meanwhile, pixel scaling efforts and microlens designs allow recovering the loss in fill factor caused by the in-pixel storage elements required in GS pixels, and allowed low-noise GS pixel design with good shutter efficiency. Shutter efficiency reports how much the stored pixel value is distorted by incoming light (which will be typically light from an unrelated exposure period which falls on the pixel when awaiting readout). It is calculated as {1 – sensitivity with shutter closed / sensitivity with shutter open} and can typically be wavelength dependent.

FIGURE 2. 5-transistor charge domain global shutter pixel (a) and 7-transistor charge domain global shutter pixel (b).

FIGURE 2. 5-transistor charge domain global shutter pixel (a) and 7-transistor charge domain global shutter pixel (b).

FIGURE 2 shows two global shutter pixels of earlier generations. Fig. 2a is a 5-transistor global shutter pixel, which stores the image on floating diffusion FD after exposure. At readout, the value sampled on FD is read through the source follower when the pixel row is selected. Then the floating diffusion is reset, and a reference level is read from the pixel. This reference level cancels any random fixed offset variations between pixels, which would otherwise cause fixed pattern noise. However, the temporal kTC noise on the floating diffusion sense node is not cancelled, since the reference for each pixel is taken after reading the photosignal, by a new reset of the sense node, which introduces a new random offset error uncorrelated to the signal level. Gate TX2 acts as an anti- blooming drain and is also used to start the exposure. The anti-blooming function is important, since excess charges are not allowed to flow to FD, where the pixel data of the previous exposure is stored.

The shutter efficiency of such pixels is not very good, typically below 99.9% for green light. The reasons why are shown in fig. 3, which is a cross-section of the 5T pixel structure. Photons generate electrons in the substrate, which diffuse through the substrate until they reach the pinned photodiode as shown in green. Some electrons generated deeper in the substrate may be collected directly by an unrelated n+ junction, such as the n+ junctions of the charge drain or the drain of the reset transistor, as shown in orange. These charges do not contribute to the photosignal and result in a loss of quantum efficiency. Some charges may diffuse to the junction of the floating diffusion, rather than by the photodiode, as shown in red. These disturb the signal stored on the floating diffusion and reduce the shutter efficiency.

This diffusion also explains the wavelength dependency of shutter efficiency for this pixel type: blue light is generated close to the surface, the majority of it inside the pinned photodiode. Part of the electrons generated by red or near infrared light are located deeper in the silicon, and have to diffuse first to the photodiode, but may reach the floating diffusion instead, which results in lower shutter efficiency for these longer wavelengths.

Often, a light shield is placed on top of the storage node to improve shutter efficiency and microlenses are used to focus the light onto the photodiode, away from the storage area. Also, a higher doped p-well under the unrelated n+ junctions can be used to reduce the charge diffusion of electrons, thanks to a small potential difference between the epitaxial p- substrate and this higher doped p-well region. A majority of the electrons will prefer to diffuse to the photodiode, where this barrier is not present.

FIGURE 3. Cross-section of a 5T charge domain global shutter pixel

FIGURE 3. Cross-section of a 5T charge domain global shutter pixel

However, a further effect that reduces shutter efficiency and which is not solved by light shields and neither by this p-well, is that some charge may leak from the photodiode through the transfer gate to the floating diffusion during the next exposure time (see Ileak in FIGURE 3). To include this effect in shutter efficiency measurements, it should be measured with constant light in a mode where the pixel integrates the next exposure during readout. Often, shutter efficiency is measured while the photodiode is drained through TX2, which cancels this transfer gate leakage, but which does not match the typical use cases for global shutter pixels in the real world, where a next image is captured during readout of the image. Furthermore, dark leakage current of the floating diffusion junction will also disturb the signal sampled on it and is a further source of noise, hot pixels and non-uniformity. This is especially important since the floating diffusion n+/p junction reaches the surface, where leakage currents will increase due to surface defects present inside the depletion region of the n+/p junction.

Fig. 2b solves the shutter efficiency and dark leakage issues of the storage node by storing the signal in voltage domain on capacitor C behind a first source follower, instead of on the floating diffusion. This capacitor can be larger and be composed of a gate or plate capacitance, which is not capable to collect electrons straight from the substrate, where they are generated by photons. In this way, the shutter efficiency can be improved above 99.98%. The pixel can be operated with double sampling by reading the reset level as a reference after reading the value sampled on C, but it still lacks correlated double sampling, just like the 5T pixel of fig. 2a. And some electrons can be collected from the substrate by the junctions of the switch connecting to the capacitor, which explains why shutter efficiency is not perfect.

For both pixel types of Fig. 2, the full well charge is proportional to the sense node capacitance, and the noise is proportional to the square root of the sense node capacitance. A typical floating diffusion of 1.6 fF, corresponding with a conversion gain of 100 μV/e-, will operate with a voltage swing of 1V. This corresponds with a saturation level of 10,000 e-. The kTC noise on 1.6 fF is 16 e- RMS. This noise appears both on the signal and reference samples, so it is increased by the square root of 2 (sqrt(2)) to 23 e- RMS at the sensor output. The dynamic range is then limited to 53 dB in this example, which is clearly lower than its IT CCD counterparts. Only if the reset level of the floating diffusion before charge transfer is used as a reference for the photosignal, it is possible to cancel the kTC noise of the sense node through CDS and reach similar dynamic range as IT CCDs.

Charge domain global shutter pixels

 FIGURE 4. CDS charge domain global shutter pixel and timing

FIGURE 4. CDS charge domain global shutter pixel and timing

FIGURE 4 shows a charge transfer pixel [1] with correlated double sampling and its timing scheme. In addition to the 5T GS pixel structure, two extra transfer gates ø2 and ø3 have been added. The signal is transferred synchronously in all pixels of the array to gate ø2 after exposure. During readout, this charge packet stored under ø2 is transferred to the floating diffusion row-by- row. The floating diffusion is sampled before and after charge transfer in a CDS scheme, and hence reducing read noise. Read noise of 4.8 e- RMS [2] and 3 e- RMS [3] have been reported with this structure. Shutter efficiency of such pixel is limited, since some photo- charges generated in the substrate may be collected directly by the storage gate ø2 rather than by the photo- diode. [3] reports a shutter efficiency of 99.96%, which is again limited by charge diffusion and leakage current under transfer gate ø1.

It is clear that CDS and global shutter require two memory elements in the pixel. In this case, the floating diffusion and gate ø2 are these two memory elements. Variants of this structure have been proposed, mainly to reduce the area required for charge transfer and storage: a combined ø1/ø2 gate with two different potentials under it [2], a compact ‘pump gate’ replacing ø1/ø2 [3] or a structure where ø2 is replaced by a pinned photo-diode [4]. Though offering the best noise performance, the shutter efficiency is not satisfactory for all applications. A second problem remains dark current leakage on the storage node ø2. This storage gate is typically a surface channel device (except in [4] where it is a pinned photodiode). For lowest leakage, the storage device should be a buried channel device. But a buried channel device has lower charge storage capacity per unit area, which may limit the minimum possible pixel size.

Voltage domain global shutter pixel

FIGURE 5 shows a GS pixel structure counting 8 transistors and two in-pixel capacitors. This is a voltage domain global shutter pixel that memorizes not only the signal level but also the reset level of the floating diffusion in the pixel on a capacitor behind the first buffer amplifier. The pixel of Fig. 5 shows two storage capacitors that are connected in series but other configurations can be considered where the storage capacitors are connected in parallel or in cascade. This series connected approach resulted in the most compact pixel design. Timing is also shown in Fig. 5. The image acquisition cycle starts with an exposure of the pinned photo- diode. At the end of the exposure period, the reset level Vreset is first sampled on C2, after which charge is trans- ferred to the floating diffusion FD. Then the signal level Vsignal is sampled on C1. During readout, first the reset level is read out from C2. Then C1 and C2 are shorted. Since C1 and C2 are equal in capacitance, the signal read after shorting both capacitors is (Vsignal + Vreset)/2. The readout circuit, present typically in the column amplifier of the image sensor, calculates the difference between both pixel readings, and amplifies the signal again so that Vsignal – Vreset results.

FIGURE 5. Voltage domain global shutter pixel with CDS

FIGURE 5. Voltage domain global shutter pixel with CDS

Fig.5 shows two timing modes. In mode 1, the S2 pulse remains on during sampling of the second sample Vsignal of the pixel. In mode 2, S2 is opened again before sampling. Mode 1 contains an asymmetric gate-source cross-talk between the two samples.

This causes an extra offset between both readings and increases fixed pattern noise by approx. 30%. However, temporal read noise is lower. It can be shown that the temporal read noise of the pixel is optimum when C1 is equal to C2. In mode 1, the temporal read noise is given by kT/2C where C is the capacitance value of C1 and C2. In mode 2, the read noise is kT/C. A more complex model including noise of in-pixel transistors has been made. Read noise depends strongly on the size of in-pixel capacitors. For larger pixels, a larger capacitance can be made, and lower read noise can be reached. A 5.5 μm pixel with two in-pixel capacitors of 16 fF each has been made, resulting in 13 and 10 e- RMS in modes 2 and 1 respectively. A larger 6.4 μm pixel with two in-pixel 36 fF capacitors reached 8 e- RMS. On a smaller 3.5 μm pixel, only 8 fF was available, resulting in a read noise of 17 e- RMS.

Full well charge of the 5.5 μm pixels is limited by the swing on the floating diffusion sense node, to about 13,500 e-. This results in a dynamic range of 60 dB for the 5.5 μm pixels. The 6.4 μm pixel reaches a full well charge of 15,000 e-, which results, together with its lower noise, in 65 dB dynamic range.

Shutter efficiency of this 8T GS pixel structure is excellent thanks to a variety of reasons:

1) the capacitors C1 and C2 are implemented through gate or metal-isolator-metal capacitors, which are unable to collect charges generated in the substrate. Some small contribution of charges collected from the substrate is still possible, through the source/drain junctions of the in-pixel switches S1 and S2. But these junctions do cover only a very small area of the pixel

2) If such charges are collected from the substrate, there is a similar chance that they are collected on C1 or on C2. This creates a common-mode offset error on both the signal and reference samples stored on both capacitors, which is cancelled after CDS.

3) An electron collected on C1 or C2 has less impact on the voltage signal than an electron present on the floating diffusion, by the ratio of the capaci- tance of the floating diffusion and the storage capacitor. For example, in the 5.5 μm pixels, the floating diffusion is 1.6 fF, and the storage capacitors are 16 fF each. This means that an electron converted on FD causes a signal change of 100 μV, while an electron collected on C1 or C2 causes only a shift of 10 μV.

The reported shutter efficiency for a front-side illumi- nated (FSI) 8T GS pixel is better than 99.999%. Because the pixel does not rely on light shields and the storage nodes are almost not capable of collecting any charges from the substrate, such pixel can also be used in combi- nation with backside thinning.

Backside illumination and global shutter pixels

Today, backside illuminated CMOS image sensors have been widely adapted in consumer applications. This technology was introduced to improve light sensitivity while pixel pitch could be further reduced, to 1.4 μm and below. The same technology can also help to improve quantum efficiency and light sensitivity of global shutter pixels. Backside illumination (BSI) can also increase the light sensitive spectrum into the near and extreme UV spectrum. These wavelengths are blocked on traditional front-side illuminated image sensors due to absorption in the inter-metal dielectric layers on top of the silicon. But these wavelengths get important in more and more machine vision applications, for example semiconductor inspection.

Since with BSI, the photocharges are generated from the backside surface onwards, charge diffuse towards the photodiode gets more important. This is why obtaining good shutter efficiency is more difficult than with front-side illumination. Light shields are not very effective, since they don’t influence charge diffusion. Also, shutter efficiency now becomes worse for shorter wavelength, since these photons are absorbed closer to the surface and generate photocharges further away from the photo-diode. In particular for the charge domain global shutter pixels discussed before, it becomes difficult to avoid diffusion to the charge storage element. A voltage domain global shutter pixel with CDS can keep its good shutter efficiency thanks to the reasons mentioned before, such as the lower impact on the signal when an electron hitting the storage element, and the differential operation of the CDS voltage domain global shutter pixel.

An 8T voltage domain global shutter BSI prototype image sensor has been made and reported [6] with a shutter efficiency of 99.996%, well above the acceptance limit for almost all use cases. Read noise and full well charge, were not changed with backside illumination. QE can be optimized to the desired wavelength range by an optimized anti-reflective coating.

Scaling of global shutter pixels

The 8T pixel structure contains a lot of compo- nents (8 transistors, 2 capacitors) and a signif- icant amount of interconnect routing. The smallest possible pixel pitch in 0.18 μm CMOS is around 5.5 μm. To develop smaller 3.5 μm pixels the following approaches were taken:

1) The IC technology is switched for a smaller geometric node. CMOSIS developed pixels in a process with 110 nm front-end and 90 nm back-end design rules. This process was initially developed for 1.75 μm shared 4T pixels and allows narrow interconnect pitch. Also the height of the interconnect stack is reduced, which improves the optical performance of the pixel such as quantum efficiency and angular pixel response.

2) Pixel sharing is employed to share the first source follower in the pixel. Interconnect routing is shared to select pixels from 2 adjacent rows to 2 vertical column busses.

More details are described in [7]. In spite of the scaling, a dynamic range of 58.5 dB is reached on a 3.5 μm global shutter pixel, with a noise level of 17 e- RMS and a full well charge of 14,800 e-. Quantum efficiency is 46% at 550 nm.


CMOS sensors with global shutter pixels can only compete with IT-CCD devices in case when the pixel allows correlated double sampling (CDS), in order to keep the temporal read noise low. Mechanisms similar to smear in a CCD cause a degradation of shutter efficiency on the global shutter pixels, which must be dealt with effectively in pixel design. One solution is a voltage domain global shutter pixel. Several pixel implementations have been discussed, and pixel specifications of voltage domain pixels are listed in TABLE 1. Charge domain pixels offer lower read noise at the cost of decreased shutter efficiency and are more difficult to use with backside illumination. Future developments in global shutter pixels use CMOS scaling for smaller pixel structures, while aiming to at least maintain performance at the values reached today. Backside illumination can be considered, and has been demonstrated already with voltage domain global shutter pixels.

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1. S. Lauxtermann, A. Lee, J. Stevens and A. Joshi, “Comparison of Global Shutter Pixels for CMOS Image Sensors”, 2007 International Image Sensor Workshop, Ogunquit, ME, June 2007 (
2. M. Sakakibara, et al, “An 83dB-Dynamic-Range Single-Expo- sure Global-Shutter CMOS Image Sensor with In-Pixel Dual Storage”, ISSCC Dig. Tech. Papers, pp. 380-381, February 2012
3. S. Velichko, et al, “Low Noise High Efficiency 3.75 μm and 2.8μm Global Shutter CMOS Pixel Arrays”, 2013 International Image Sensor Workshop, Snowbird, Utah, June 2013 (www.
4. K. Yasutomi, et al, “A Two-Stage Charge Transfer Active Pixel CMOS Image Sensor With Low-Noise Global Shuttering and a Dual-Shuttering Mode”, IEEE Trans. El. Dev., Vol. 58, No. 3, March 2011
5. G. Meynants, “Global shutter pixels with correlated double sampling for CMOS image sensors”, Adv. Opt. Techn. 2013; (2): pp. 177-187
6. G. Meynants, et al, “Backside illuminated Global Shutter CMOS Image Sensors”, 2011 International Image Sensor Workshop, Hokkaido, Japan, June 2011 (www.imagesensors. org)
7.B.Wolfs,etal,“3.5μmglobalshutterpixelwithtransistor sharing and correlated double sampling”, 2013 International Image Sensor Workshop, Snowbird, Utah, June 2013 (www.


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