“Fan-Out Wafer Level Packaging (FOWLP) is already in high-volume” announces Yole Développement (Yole) in its new report, Fan-Out and Embedded Die: Technologies & Market. According to Yole’s analysts, FOWLP market reaches almost $200M in 2015. And the More than Moore market research and strategy consulting company, Yole expects 30% CAGR in the coming years. What can explain such a great potential?
Fan-Out Wafer Level Packaging (FOWLP) started volume commercialization in 2009/2010 and started promisingly, with initial push by Intel Mobile. However, it was limited to a narrow range of applications, essentially single die packages for cell phone baseband chips. But this growth reached its limit in 2011. And in 2012 big fab-less wireless/mobile players started slowly volume production after qualifying the technology.
It faced strong competition from other packaging technologies, such as wafer-level chip scale packaging (WLCSP) in 2013/2014. Intel Mobile also backed off from the technology, and the main manufacturers reduced their prices in 2014, creating a transition phase with low market growth.
Today, according to Fan-Out and Embedded Dies: Technologies & Market Trends report, Yole’s analysts now expect strong growth. They explain: “The market is worth almost $200M and we anticipate 30% CAGR is in coming years”. One of the key factors driving this is the arrival of 2nd generation FOWLP. More customers are also being convinced, a wider range of potential applications reached, and technology qualifications started during the transition phase completed by strong fabless players.
What can explain such great potential? Primarily, mobile customers have high expectations of miniaturization and higher integration while keeping costs low. This leads naturally to WLP for cost and performance and system-in-package (SiP) solutions for integration and functionality. FOWLP has proven its ability to reach these targets. Its small form-factor and low cost potential shown in the 1st generation are now enhanced with high-integration capability of the 2nd generation.
“Benefiting from the delay in introducing 3D through-silicon via (TSV) architectures, FOWLP is currently seen as the best fit for the highly demanding mobile/wireless market and is attractive for other markets focusing on high performance and small size”, explains Jérôme Azemar, Technology & Market Analyst, Advanced Packaging & Manufacturing, Yole Développement.
Under this technology & market report, Yole provides a complete overview of the different market expectations and a detailed application-by-application breakdown. The company also describes the different strategies and products of each player involved in FOWLP, from the main outsourced assembly and test companies, like STATS ChipPAC and Nanium, to foundries like TSMC. Since cost is always the first driver, the report also focuses on equipment and material challenges and substrate size evolution, both for wafers and panels.